HT48R05A-1/HT48C05/HT48R06A-1/HT48C06/HT48R08A-1
signal in output mode of PB0/PB1 will be the PFD signal
Low Voltage Reset - LVR
generated by timer/event counter overflow signal. The
input mode always remaining its original functions.
Once the BZ/BZ option is selected, the buzzer output
signals are controlled by PB0 data register only. The I/O
functions of PB0/PB1 are shown below.
The microcontroller provides low voltage reset circuit in
order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~VLVR, such as changing a battery, the LVR will au-
tomatically reset the device internally.
PB0 I/O
I
I
I
I
O
B
0
x
I
O
B
1
x
O
I
O O O
O
O
B
0
O
O
B
1
The LVR includes the following specifications:
PB1 I/O
O
C
x
I
B
0
x
0
I
I
O
C
·
The low voltage (0.9V~VLVR) has to remain in their
original state to exceed 1ms. If the low voltage state
does not exceed 1ms, the LVR will ignore it and do not
perform a reset function.
PB0/PB1 Mode
PB0 Data
x
x
x
I
C
D
x
B
1 D0
x D1
B D0
·
The LVR uses the ²OR² function with the external
RES signal to perform chip reset.
PB1 Data
D
I
x
x
PB0 Pad Status
PB1 Pad Status
I
I
D
I
0
B
B
The relationship between VDD and VLVR is shown below.
I
D
0
B
I
D1
0
V
D
D
V
O P R
5
.
5
V
5
.
5
V
Note: I: input; O: output; D, D0, D1: data;
B: buzzer option, BZ or BZ; x: don't care
C: CMOS output
V
L
V
R
The PC0 and PC1 are pin-shared with INT, TMR and
pins respectively.
3
.
0
V
2
.
2
V
It is recommended that unused or not bonded out I/O
lines should be set as output pins by software instruction
to avoid consuming power under input floating state.
0
.
9
V
VOPR is the voltage range for proper chip opera-
tion at 4MHz system clock.
Note:
V
D
D
5
.
5
V
L
V
R
D
e
t
e
c
t
V
o
l
t
a
g
e
V
L
V
R
0
.
9
0
V
V
R
e
s
e
t
S
i
g
n
a
l
R
e
s
e
t
N
o
r
m
a
l
O
p
e
r
a
t
i
o
n
R
e
s
e
t
*
1
*
2
Low Voltage Reset
Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of
1024 system clock pulses before entering the normal operation.
*2: Since low voltage has to be maintained in its original state and exceed 1ms, therefore 1ms
delay enters the reset mode.
Rev. 1.50
15
August 22, 2007
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
