HT46R47-H
During the execution of an interrupt subroutine, other in-
terrupt acknowledgments are held until the RETI in-
struction is executed or the EMI bit and the related
interrupt control bit are set to 1 (of course, if the stack is
not full). To return from the interrupt subroutine, RET or
RETI may be invoked. RETI will set the EMI bit to enable
an interrupt service, but RET will not.
Oscillator Configuration
There are two oscillator circuits in the microcontroller.
V
D
D
O
S
C
1
O
S
C
1
S
Y
S
O
S
C
2
O
S
C
2
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
N
M
O
S
O
p
e
n
D
r
a
i
n
C
r
y
s
t
a
l
O
s
c
i
l
l
a
t
o
r
R
C
O
s
c
i
l
l
a
t
o
r
System Oscillator
Both are designed for system clocks, namely the RC os-
cillator and the Crystal oscillator, which are determined
by the options. No matter what oscillator type is se-
lected, the signal provides the system clock. The HALT
mode stops the system oscillator and ignores an exter-
nal signal to conserve power.
Interrupt Source
External Interrupt
Priority
Vector
04H
1
2
3
Timer/Event Counter Overflow
A/D Converter Interrupt
08H
If an RC oscillator is used, an external resistor between
OSC1 and VSS is required and the resistance must
range from 30kW to 750kW. The system clock, divided
by 4, is available on OSC2, which can be used to syn-
chronize external logic. The RC oscillator provides the
most cost effective solution. However, the frequency of
oscillation may vary with VDD, temperatures and the
chip itself due to process variations. It is, therefore, not
suitable for timing sensitive operations where an accu-
rate oscillator frequency is desired.
0CH
The timer/event counter interrupt request flag (TF), ex-
ternal interrupt request flag (EIF), A/D converter request
flag (ADF), enable timer/event counter bit (ETI), enable
external interrupt bit (EEI), enable A/D converter inter-
rupt bit (EADI) and enable master interrupt bit (EMI)
constitute an interrupt control register (INTC) which is
located at 0BH in the data memory. EMI, EEI, ETI, EADI
are used to control the enabling/disabling of interrupts.
These bits prevent the requested interrupt from being
serviced. Once the interrupt request flags (TF, EIF, ADF)
are set, they will remain in the INTC register until the in-
terrupts are serviced or cleared by a software instruc-
tion.
If the Crystal oscillator is used, a crystal across OSC1
and OSC2 is needed to provide the feedback and phase
shift required for the oscillator, and no other external
components are required. Instead of a crystal, a resona-
tor can also be connected between OSC1 and OSC2 to
get a frequency reference, but two external capacitors in
OSC1 and OSC2 are required (If the oscillating fre-
quency is less than 1MHz).
It is recommended that a program does not use the CALL
subroutine within the interrupt subroutine. Interrupts of-
ten occur in an unpredictable manner or need to be ser-
viced immediately in some applications. If only one stack
is left and enabling the interrupt is not well controlled, the
original control sequence will be damaged once the
²CALL² operates in the interrupt subroutine.
The WDT oscillator is a free running on-chip RC oscilla-
tor, and no external components are required. Even if
the system enters the power down mode, the system
clock is stopped, but the WDT oscillator still works with a
period of approximately 65ms at 5V. The WDT oscillator
can be disabled by options to conserve power.
Bit No.
Label
EMI
EEI
Function
0
1
2
3
4
5
6
Controls the master (global) interrupt (1=enabled; 0=disabled)
Controls the external interrupt (1=enabled; 0=disabled)
Controls the Timer/Event Counter interrupt (1=enabled; 0=disabled)
Controls the A/D converter interrupt (1=enabled; 0=disabled)
External interrupt request flag (1=active; 0=inactive)
ETI
EADI
EIF
TF
Internal Timer/Event Counter request flag (1=active; 0=inactive)
A/D converter request flag (1=active; 0=inactive)
ADF
For test mode used only.
7
¾
Must be written as ²0²; otherwise may result in unpredictable operation.
INTC (0BH) Register
Rev. 1.30
11
March 1, 2006
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
