HT46R46/C46/R47/C47/R48A/C48A/R49
Pin Assignment
P
A
3
/
P
F
D
P
A
4
/
/
T
I
M
R
P
B
4
P
B
5
2
1
1
1
1
1
1
1
1
1
0
9
8
7
6
5
4
3
2
1
2
1
1
1
1
1
1
1
1
1
0
9
8
7
6
5
4
3
2
1
1
2
3
4
5
6
7
8
9
1
1
2
3
4
5
6
7
8
9
1
P
A
3
/
P
F
D
P
P
P
P
O
O
V
A
A
A
A
4
5
6
7
/
T
M
R
P
A
2
P
A
5
N
T
P
A
3
/
P
F
D
P
A
4
/
/
T
I
M
R
1
2
3
4
5
6
7
8
9
1
1
1
1
1
1
1
1
1
8
7
6
5
4
3
2
1
0
P
A
3
/
P
F
D
P
P
P
A
4
/
T
I
M
R
P
A
2
/
I
N
T
P
P
A
A
1
P
A
A
6
7
P
P
P
A
A
A
2
1
0
3
2
1
0
P
A
5
N
T
1
2
3
4
5
6
7
8
1
1
1
1
1
1
1
6
5
4
3
2
1
0
9
P
A
2
A
5
/
N
T
P
P
A
A
1
0
0
3
P
P
A
A
6
7
P
B
3
/
A
N
O
S
S
C
C
2
1
P
P
P
A
A
1
0
A
A
6
7
S
C
2
1
P
B
3
/
A
N
3
N
C
O
P
B
3
/
A
N
O
O
V
R
P
S
S
C
C
2
1
P
S
C
P
P
B
B
2
1
/
/
A
A
N
N
2
1
V
D
D
P
P
B
B
2
1
/
/
A
A
N
N
P
B
1
/
A
N
1
O
O
V
S
C
2
1
P
B
2
/
A
N
2
D
D
S
C
R
E
S
0
D
D
S
0
P
P
B
B
1
0
/
/
A
A
N
N
1
0
P
B
0
/
A
N
0
P
B
0
/
A
N
0
P
N
D
/
P
W
M
P
B
0
/
A
N
E
V
S
S
D
D
R
P
E
S
0
V
S
S
C
V
S
S
D
/
P
W
M
P
D
0
/
P
W
M
V
S
S
D
/
P
W
M
R
E
S
0
0
H
T
4
6
R
4
6
/
H
T
4
6
C
4
6
H
T
4
6
R
4
6
/
H
T
4
6
C
4
6
H
T
4
6
R
4
6
/
H
T
4
6
C
4
6
H
T
4
6
R
4
8
A
/
H
T
4
6
C
4
8
A
H
T
4
6
R
4
N
7
/
H
O
T
4
6
C
4
7
H
T
4
6
R
4
7
/
H
T
4
6
C
4
7
H
T
4
6
R
4
7
/
H
T
4
6
C
4
7
2
0
D
I
P
-
A
/
S
O
P
-
A
1
6
S
P
-
A
1
8
D
I
P
-
A
/
S
O
P
-
A
2
0
S
S
O
P
-
A
P
P
B
B
5
4
1
2
3
4
5
6
7
8
9
1
1
1
1
1
2
2
2
2
2
2
2
2
2
1
1
1
1
1
8
7
6
5
4
3
2
1
0
9
8
7
6
5
P
B
6
P
B
7
P
P
B
B
5
4
P
A
3
/
P
F
D
P
A
4
/
/
T
I
M
R
P
P
B
B
5
4
1
2
3
4
5
6
7
8
9
1
1
1
P
P
P
P
P
P
O
O
V
R
P
P
B
B
A
A
A
A
6
7
4
5
6
7
1
2
3
4
5
6
7
8
9
1
1
1
P
B
6
2
2
2
2
2
1
1
1
1
1
1
1
4
3
2
1
0
9
8
7
6
5
4
3
2
2
2
2
2
1
1
1
1
1
1
1
4
3
2
1
0
9
8
7
6
5
4
3
P
P
P
A
A
A
2
1
0
P
A
5
N
T
P
B
7
P
A
3
/
P
F
D
P
A
4
/
/
T
I
M
R
2
1
1
1
1
1
1
1
1
1
0
9
8
7
6
5
4
3
2
1
P
A
3
/
P
F
D
P
A
A
6
7
P
A
3
/
P
F
D
/
/
T
I
M
R
P
A
4
/
/
T
I
M
R
1
2
3
4
5
6
7
8
9
1
P
P
A
A
2
P
A
5
N
T
P
P
P
A
A
A
2
P
P
P
P
A
A
A
2
1
0
3
2
1
0
N
T
P
A
5
N
T
1
P
A
A
6
7
1
P
P
P
P
B
B
B
B
3
2
1
0
/
/
/
/
A
A
A
A
N
N
N
N
3
2
1
0
O
S
S
C
C
2
1
P
P
O
O
V
R
P
P
A
A
6
7
P
A
0
P
0
O
P
B
3
/
A
N
3
O
S
S
C
C
2
1
P
B
3
/
A
N
3
V
D
D
P
P
P
P
B
B
B
B
3
2
1
0
/
/
/
/
A
A
A
A
N
N
N
N
S
C
2
1
S
C
2
1
P
B
2
/
A
N
2
O
P
B
2
/
A
N
2
0
1
2
3
4
R
E
S
S
C
S
C
P
P
B
B
1
0
/
/
A
A
N
N
1
0
V
D
D
P
P
B
B
1
0
/
/
A
A
N
N
1
0
V
S
S
P
D
1
/
/
P
P
W
W
M
M
1
0
D
D
D
D
S
1
0
R
E
S
P
P
C
C
0
1
P
D
0
0
1
2
E
S
0
1
2
E
V
S
S
P
P
D
D
1
0
/
/
P
P
W
W
M
M
1
0
P
P
C
C
V
S
S
D
C
0
1
/
P
W
M
V
S
S
D
D
/
/
P
P
W
W
M
M
1
0
4
3
P
C
0
P
C
0
P
C
2
P
C
0
0
H
T
4
6
R
4
8
A
/
H
T
4
6
C
4
8
A
H
T
4
6
R
4
9
H
T
4
6
R
4
9
H
T
4
6
R
4
9
2
4
S
K
D
I
P
-
A
/
S
O
P
-
A
/
S
S
O
P
-
A
2
0
D
I
P
-
A
/
S
O
P
-
A
2
4
S
K
D
I
P
-
B
/
S
O
P
-
B
2
8
S
K
D
I
P
-
A
/
S
O
P
-
A
Pin Description
HT46R46, HT46R47
Configuration
Option
Pin Name I/O
Description
PA0~PA2
PA3/PFD
Bidirectional 8-bit input/output port. Each individual pin on this port can be config-
ured as a wake-up input by a configuration option. Software instructions determine
if the pin is a CMOS output or Schmitt Trigger input. Configuration options deter-
Pull-high
Wake-up
PA4/TMR I/O
PA5/INT
PA3 or PFD mine which pins on the port have pull-high resistors. Pins PA3, PA4 and PA5 are
pin-shared with PFD, TMR and INT, respectively.
PA6~PA7
Bidirectional 4-bit input/output port. Software instructions determine if the pin is a
CMOS output or Schmitt Trigger input. Configuration options determine which pins
PB0/AN0
PB1/AN1
I/O
Pull-high
on the port have pull-high resistors. PB is pin-shared with the A/D input pins. The
A/D inputs are selected via software instructions. Once selected as an A/D input,
the I/O function and pull-high resistor options are disabled automatically.
PB2/AN2
PB3/AN3
Bidirectional 1-bit input/output port. Software instructions determine if the pin is a
CMOS output or Schmitt Trigger input.
Pull-high
PD0/PWM I/O
PD0 or PWM A configuration option determines if this pin has a pull-high resistor. The PWM out-
put is pin-shared with pin PD0 selected via a configuration option.
OSC1, OSC2 are connected to an external RC network or external crystal, deter-
OSC1
OSC2
I
Crystal
mined by configuration option, for the internal system clock. If the RC system clock op-
or RC
O
tion is selected, pin OSC2 can be used to measure the system clock at 1/4 frequency.
RES
VDD
VSS
I
Schmitt Trigger reset input. Active low.
¾
Positive power supply
¾
¾
¾
Negative power supply, ground
¾
Note: 1. Each pin on PA can be programmed through a configuration option to have a wake-up function.
2. Individual pins can be selected to have a pull-high resistor.
3. Pins PB2/AN2~PB3/AN3 exist but are not bonded out on the 16-pin package.
4. unbonded pins should be setup as outputs or as inputs with pull-high resistors to conserve power.
Rev. 1.30
3
June 5, 2008
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
