HT46R14A
abled until the TBLH has been backed up. All table re-
lated instructions require two cycles to complete the
operation. These areas may function as normal pro-
gram memory depending upon requirements.
Stack Register
-
STACK
This is a special part of the memory which is used to
save the contents of the program counter only. The
stack is organized into 8 levels and is neither part of the
data nor part of the program space, and is neither read-
able nor writeable. The activated level is indexed by the
stack pointer, SP, and is neither readable nor writeable.
At a subroutine call or interrupt acknowledge signal, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
indicated by a return instruction, RET or RETI, the pro-
gram counter is restored to its previous value from the
stack. After a chip reset, the SP will point to the top of the
stack.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledge signal will be inhibited. When the stack
pointer is decremented, using RET or RETI, the inter-
rupt will be serviced. This feature prevents a stack over-
flow allowing the programmer to use the structure more
easily. In a similar case, if the stack is full and a
²CALL²
is subsequently executed, a stack overflow will occur
and the first entry will be lost as only the most recent 8
return addresses are stored.
Data Memory
-
RAM
The data memory has a capacity of 224´8 bits, and is
divided into two functional groups, namely the special
function registers and the general purpose data mem-
ory (192´8 bits), most of which are readable/writeable,
although some are read only.
The unused space before address 40H is reserved for
future expansion usage and reading these locations will
obtain a result of
²00H².
The general purpose data
memory, addressed from 40H to FFH is used for data
and control information under instruction commands.
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations di-
rectly. Except for some dedicated bits, each bit in the
data memory can be set and reset by
²SET
[m].i² and
²CLR
[m].i². They are also indirectly accessible through
the memory pointer registers, MP0 and MP1.
0 0 H
0 1 H
0 2 H
0 3 H
0 4 H
0 5 H
0 6 H
0 7 H
0 8 H
0 9 H
0 A H
0 B H
0 C H
0 D H
0 E H
0 F H
1 0 H
1 1 H
1 2 H
1 3 H
1 4 H
1 5 H
1 6 H
1 7 H
1 8 H
1 9 H
1 A H
1 B H
1 C H
1 D H
1 E H
1 F H
2 0 H
2 1 H
2 2 H
2 3 H
2 4 H
2 5 H
2 6 H
2 7 H
2 8 H
3 F H
4 0 H
P P G 0 C
P P G T 0
P P G 1 C
P P G T 1
A D R L
A D R H
A D C R
A C S R
M F IC
C M P 0 C
C M P 1 C
IN T C 1
T M R 1
T M R 1 C
P A
P A C
P B
P B C
P C
P C C
S p e c ia l P u r p o s e
D a ta M e m o ry
T M R 0
T M R 0 C
S T A T U S
IN T C 0
A C C
P C L
T B L P
T B L H
In d ir e c t A d d r e s s in g R e g is te r 0
M P 0
In d ir e c t A d d r e s s in g R e g is te r 1
M P 1
F F H
G e n e ra l P u rp o s e
D a ta M e m o ry
(1 9 2 B y te s )
: U n u s e d
R e a d a s "0 0 "
RAM Mapping
Rev. 1.00
8
August 3, 2007
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
