HT46R14
17H), the programmable pulse generator0 (PPG0)
control register (PPG0C;20H), the programmable
pulse generator timer register (PPGT0;21H), the pro-
grammable pulse generator1 (PPG1) control register
(PPG1C;22H), the programmable pulse generator
timer register (PPGT1;23H).
The remaining space before the 40H is reserved for fu-
ture expanded usage and reading these locations will
get
²00H².
The general purpose data memory, ad-
dressed from
²40H²
to
²FFH²,
is used for data and con-
trol information under instruction commands.
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations di-
rectly. Except for some dedicated bits, each bit in the
data memory can be set and reset by
²SET
[m].i² and
²CLR
[m].i². They are also indirectly accessible through
memory pointer registers (MP0;01H/MP1;03H).
Indirect Addressing Register
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write op-
eration of [00H] and [02H] accesses the RAM pointed to
by MP0(01H) and MP1(03H) respectively. Reading lo-
cation 00H or 02H indirectly returns the result 00H.
While, writing it indirectly leads to no operation.
The function of data movement between two indirect ad-
dressing registers is not supported. The memory pointer
registers, MP0 and MP1, are both 8-bit registers used to
access the RAM by combining corresponding indirect
addressing registers.
Accumulator
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the data memory and
can carry out immediate data operations. The data
movement between two data memory locations must
pass through the accumulator.
Arithmetic and Logic Unit
-
ALU
This circuit performs 8-bit arithmetic and logic operations.
The ALU provides the following functions:
·
Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
·
Logic operations (AND, OR, XOR, CPL)
·
Rotation (RL, RR, RLC, RRC)
·
Increment and Decrement (INC, DEC)
·
Branch decision (SZ, SNZ, SIZ, SDZ)
0 0 H
0 1 H
0 2 H
0 3 H
0 4 H
0 5 H
0 6 H
0 7 H
0 8 H
0 9 H
0 A H
0 B H
0 C H
0 D H
0 E H
0 F H
1 0 H
1 1 H
1 2 H
1 3 H
1 4 H
1 5 H
1 6 H
1 7 H
1 8 H
1 9 H
1 A H
1 B H
1 C H
1 D H
1 E H
1 F H
2 0 H
2 1 H
2 2 H
2 3 H
2 4 H
2 5 H
2 6 H
2 7 H
2 8 H
4 0 H
3 F H
P P G 0 C
P P G T 0
P P G 1 C
P P G T 1
A D R L
A D R H
A D C R
A C S R
IN T C 1
T M R 1
T M R 1 C
P A
P A C
P B
P B C
P C
P C C
S p e c ia l P u r p o s e
D a ta M e m o ry
T M R 0
T M R 0 C
S T A T U S
IN T C 0
A C C
P C L
T B L P
T B L H
In d ir e c t A d d r e s s in g R e g is te r 0
M P 0
In d ir e c t A d d r e s s in g R e g is te r 1
M P 1
F F H
G e n e ra l P u rp o s e
D a ta M e m o ry
(1 9 2 B y te s )
: U n u s e d
R e a d a s "0 0 "
RAM Mapping
(TO). It also records the status information and controls
the operation sequence.
With the exception of the TO and PDF flags, bits in
the status register can be altered by instructions like
most other registers. Any data written into the status
register will not change the TO or PDF flag. In addi-
tion operations related to the status register may give
different results from those intended. The TO flag
can be affected only by system power-up, a WDT
time-out or executing the
²CLR
WDT² or
²HALT²
in-
The ALU not only saves the results of a data operation but
also changes the status register.
Status Register
-
STATUS
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF), and watchdog time-out flag
Rev. 1.20
8
February 24, 2006
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
