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Watchdog Timer
If the WDT oscillator is disabled, the WDT clock may still
be sourced from the instruction clock and operate in the
same manner except that in the Power-down mode the
WDT will stop counting and lose its protecting purpose.
In this situation the device can only be restarted by ex-
ternal logic. If the device operates in a noisy environ-
ment, using the internal WDT oscillator is strongly
recommended, since the Power-down mode will stop
the system clock.
The system can leave the Power-down mode by means
of an external reset, an interrupt, an external falling
edge signal on port A or a WDT overflow. An external re-
set causes a device initialisation and the WDT overflow
performs a ²warm reset². After the TO and PDF flags
are examined, the reason for the device reset can be de-
termined.
The PDF flag is cleared by a system power-up or exe-
cuting the ²CLR WDT² instruction and is set when exe-
cuting the ²HALT² instruction. The TO flag is set if a
WDT time-out occurs, and causes a wake-up that only
resets the program counter and the stack pointer, the
other circuits will maintain their original status.
The WDT overflow under normal operation will initialise a
device reset and set the status bit TO. In the Power-down
mode, the overflow will initialise a warm reset where only
the program counter and stack pointer are reset to 0. To
clear the WDT contents, three methods are adopted; ex-
ternal reset (a low level to RES), software instructions, or a
HALT instruction. The software instructions include CLR
WDT and the other set - CLR WDT1 and CLR WDT2. Of
these two types of instruction, only one can be active de-
pending on the options - ²CLR WDT times selection op-
tion². If the ²CLR WDT² is selected (i.e. CLRWDT times
equal 1), any execution of the CLR WDT instruction will
clear the WDT. If the ²CLR WDT1² and ²CLR WDT2² op-
tion is selected (i.e. CLRWDT times equal two), these two
instructions must be executed to clear the WDT, other-
wise, the WDT will reset the chip due to a time-out.
A port A wake-up and interrupt methods can be consid-
ered as a continuation of normal execution. Each bit in
port A can be independently selected to wake up the de-
vice, setup via configuration options. Awakening from
an I/O port stimulus, the program will resume execution
at the next instruction. If it is awakening from an inter-
rupt, two sequences may occur. If the related interrupt is
disabled or the interrupt is enabled but the stack is full,
the program will resume execution at the next instruc-
tion. If the interrupt is enabled and the stack is not full,
the regular interrupt response takes place. If an interrupt
request flag is set to ²1² before entering the
Power-down mode, the wake-up function of the related
interrupt will be disabled. Once a wake-up event occurs,
it takes 1024 system clock periods to resume normal op-
eration. In other words, a dummy period will be inserted
after the wake-up. If the wake-up results from an inter-
rupt acknowledge, the actual interrupt subroutine exe-
cution will be delayed by one or more cycles. If the
wake-up results in the next instruction execution, this
will be executed immediately after the dummy period is
finished.
Power Down Operation - HALT
The Power-down mode is entered by the execution of a
²HALT² instruction and results in the following:
·
The system oscillator will be turned off but the WDT
oscillator will keep running, if the WDT is enabled and
if its clock is sourced from the internal WDT oscillator.
·
·
The contents of the Data Memory and registers re-
main unchanged.
The WDT will be cleared and will start counting again,
if the WDT clock is sourced from the internal WDT os-
cillator.
To minimise power consumption, all the I/O pins should
be carefully managed before entering the Power-down
mode.
·
·
All of the I/O ports maintain their original status.
The PDF flag is set and the TO flag is cleared.
Rev. 1.00
12
August 3, 2007
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
