HT46R12A
Block Diagram
P r e s c a le r
U
X
T M R 0
T M R 1
U
X
f
S
Y S
In te rru p t
C ir c u it
S ta c k
P ro g ra m
C o u n te r
T M R 0 C
T M R 0
P F D 0
T M R 1 C
T M R 1
P F D 1
M
M
f
S
Y S
P ro g ra m
R O M
IN T C
/4
In s tr u c tio n
R e g is te r
W D T
M P
M
U
X
D a ta
M e m o ry
P P G 0 C
P P G T 0
P P G
M
U
f
S
X
Y S
/4
W D T O S C
P r e s c a le r
f
S
Y S
In s tr u c tio n
D e c o d e r
A L U
T im in g
G e n e ra to r
M U X
S T A T U S
P C
P C C
P o rt C
S h ifte r
4 -C h a n n e l
A /D C o n v e rte r
P C
P C
P C
P C
P C
0 /C
1 /C
2 /C
3 /C
4 /C
0 V
0 V
0 O
1 O
1 V
IN
IN
U
U
IN
T
T
-
+
-
O S C 2
O S
R E
V D
V S
S
S
D
C 1
A C C
P B
H A L T
E N /D IS
P B C
P o rt B
P B 0 /A N 0 ~ P B 3 /A N 3
L V R
P P G
P P G 0 C
P P G
P A
P A C
P o rt A
P A
P A
P A
P A
P A
0 ~ P
3 /P
4 /T
5 , P
7 /T
A 2
F D
M R 0
A 6
M R 1
Pin Assignment
P B 1 /A N 1
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
P B 0 /A N 0
P A 3 /P F D
P A 2
P A 1
P A 0
C 1 V IN +
P C 4 /C 1 V IN -
P C 3 /C 1 O U T
P C 2 /C 0 O U T
V S S
P C 1 /C 0 V IN +
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
P B 2 /A N 2
P B 3 /A N 3
P A 4 /T M R 0
P A 5
P A 6
P A 7 /T M R 1
O S C 2
O S C 1
V D D
R E S
P P G
P C 0 /C 0 V IN -
H T 4 6 R 1 2 A
2 4 S K D IP -A /S O P -A
Rev. 1.01
2
December 29, 2008
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
