HT46R01/HT46R02/HT46R03
Test Conditions
Conditions
Symbol
Parameter
I/O Port Source Current
Pull-high Resistance
Min.
Typ.
Max.
Unit
VDD
3V
5V
3V
5V
¾
mA
mA
kW
-2
-5
20
10
0
-4
-10
60
¾
¾
IOH
V
OH=0.9VDD
100
50
RPH
¾
¾
30
kW
VAD
EAD
DNL
INL
VDD
A/D Input Voltage
V
¾
ADC Conversion Error
ADC Differential Non-linear
ADC Integral Non-linear
8, 9 bit ADC
LSB
LSB
LSB
mA
mA
¾
¾
¾
¾
¾
¾
±0.5
¾
±1
±2
±4
1
¾
12 bit ADC, tAD=1ms
12 bit ADC, tAD=1ms
¾
±2.5
0.5
1.5
3V
5V
IADC
No load, tAD=1ms
ADC Power Consumption
3
A.C. Characteristics
Ta=25°C
Test Conditions
Conditions
2.2V~5.5V
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
¾
400
400
400
4000
8000
kHz
kHz
¾
¾
¾
System Clock
fSYS1
3.3V~5.5V
¾
(Crystal OSC, RC OSC)
4.5V~5.5V
12000 kHz
¾
4.5V~
5.5V
11400 12000 12600 kHz
12MHz, Ta=25°C
8MHz, Ta=25°C
4MHz, Ta=25°C
System Clock
(Internal RC OSC)
(±5%)
3.3V~
5.5V
fSYS2
7600 8000 8400
3800 4000 4200
kHz
kHz
2.7V~
5.5V
fSYS3
System Clock (32768 Crystal)
Timer I/P Frequency (TMR)
32768
¾
Hz
¾
¾
¾
¾
3V
5V
¾
¾
¾
¾
¾
¾
0
¾
2.2V~5.5V
4000
8000
kHz
kHz
fTIMER
3.3V~5.5V
0
¾
4.5V~5.5V
0
12000 kHz
¾
45
32
1
90
180
130
¾
¾
ms
ms
tWDTOSC
Watchdog Oscillator Period
65
¾
tRES
tSST
tINT
External Reset Low Pulse Width
System Start-up Timer Period
Interrupt Pulse Width
¾
¾
ms
tSYS
Wake-up from Power Down
1024
¾
¾
1
¾
¾
¾
¾
ms
tLVR
Low Voltage Width to Reset
0.25
1
2
ms
VDD Start Voltage to Ensure
Power-on Reset
VPOR
100
mV
¾
¾
¾
¾
¾
¾
VDD Rise Time to Ensure
Power-on Reset
RPOR
tAD
0.035
V/ms
¾
¾
¾
ADC Clock Period
1
¾
8 bit ADC
9 bit ADC
12 bit ADC
¾
¾
64
76
80
32
¾
¾
¾
¾
¾
ms
tAD
tAD
tAD
tAD
¾
¾
¾
¾
tADC
ADC Conversion Time
ADC Sampling Time
¾
¾
tADS
Note: tSYS=1/fSYS1, 1/fSYS2 or 1/fSYS3
Rev. 1.00
5
September 21, 2007