HT46R01/HT46R02/HT46R03
suring that the mode select bits in the Timer/Event
Counter control register, select either the event counter
or pulse width measurement mode. Additionally the cor-
responding PAC Port Control Register bits must be set
high to ensure that the pins are setup as inputs. Any
pull-high resistor register options on these pins will re-
main valid even if the pin is used as a Timer/Event
Counter input.
Programmable Frequency Divider - PFD
The PFD output is pin-shared with the I/O pin PA1. The
PFD on/off function and its timer source are selected via
bits in the CTRL0 register, however, if not selected, the
pin can operate as a normal I/O pin. The timer overflow
signal is the clock source for the PFD circuit. The output
frequency is controlled by loading the required values
into the timer register and if available the timer prescaler
registers to give the required frequency. The timer/event
counter, driven by the system clock and if applicable, di-
vided by the prescaler value, will begin to count-up from
this preloaded register value until full, at which point an
overflow signal will be generated, causing the PFD out-
put to change state. The counter will then be automati-
cally reloaded with the preload register value and once
again continue counting-up.
Programming Considerations
When configured to run in the timer mode, the internal
system clock is used as the timer clock source and is
therefore synchronised with the overall operation of the
microcontroller. In this mode when the appropriate timer
register is full, the microcontroller will generate an inter-
nal interrupt signal directing the program flow to the re-
spective internal interrupt vector. For the pulse width
measurement mode, the internal system clock is also
used as the timer clock source but the timer will only run
when the correct logic condition appears on the external
timer input pin. As this is an external event and not syn-
chronised with the internal timer clock, the
microcontroller will only see this external event when the
next timer clock pulse arrives. As a result, there may be
small differences in measured values requiring pro-
grammers to take this into account during programming.
The same applies if the timer is configured to be in the
event counting mode, which again is an external event
and not synchronised with the internal system or timer
clock.
For the PFD output to function, it is essential that the
corresponding bit of the Port A control register PAC bit 1
is setup as an output. If setup as an input the PFD output
will not function, however, the pin can still be used as a
normal input pin. The PFD output will only be activated if
bit PA1 is set to ²1². This output data bit is used as the
on/off control bit for the PFD output. Note that the PFD
output will be low if the PA1 output data bit is cleared to
²0².
Using this method of frequency generation, and if a
crystal oscillator is used for the system clock, very pre-
cise values of frequency can be generated.
Prescaler
When the Timer/Event Counter is read, or if data is writ-
ten to the preload register, the clock is inhibited to avoid
errors, however as this may result in a counting error, this
should be taken into account by the programmer. Care
must be taken to ensure that the timers are properly in-
itialised before using them for the first time. The associ-
ated timer enable bits in the interrupt control register must
be properly set otherwise the internal interrupt associated
with the timer will remain inactive. The edge select, timer
mode and clock source control bits in timer control regis-
ter must also be correctly set to ensure the timer is prop-
erly configured for the required application. It is also
important to ensure that an initial value is first loaded into
Bits T0PSC0~T0PSC2 of the TMR0C register can be
used to define a division ratio for the internal clock
source of Timer/Event Counter 0 enabling longer time
out periods to be setup.
I/O Interfacing
The Timer/Event Counters, when configured to run in
the event counter or pulse width measurement mode,
require the use of the external timer pins for their opera-
tion. As these pins are shared pins they must be config-
ured correctly to ensure that they are setup for use as
Timer/Event Counter input pins. This is achieved by en-
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PFD Output Control
Rev. 1.00
22
September 21, 2007
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
