HT46R002/HT46R003
Cost-Effective A/D 8-Bit OTP MCU
System Architecture
Aꢀkeyꢀfactorꢀinꢀtheꢀhigh-performanceꢀfeaturesꢀofꢀtheꢀHoltekꢀrangeꢀofꢀmicrocontrollersꢀisꢀattributedꢀ
toꢀtheꢀinternalꢀsystemꢀarchitecture.ꢀTheꢀrangeꢀofꢀdevicesꢀtakeꢀadvantageꢀofꢀtheꢀusualꢀfeaturesꢀfoundꢀ
withinꢀRISCꢀmicrocontrollersꢀprovidingꢀincreasedꢀspeedꢀofꢀoperationꢀandꢀenhancedꢀperformance.ꢀ
Theꢀpipeliningꢀschemeꢀisꢀimplementedꢀinꢀsuchꢀaꢀwayꢀthatꢀinstructionꢀfetchingꢀandꢀinstructionꢀ
executionꢀareꢀoverlapped,ꢀhenceꢀinstructionsꢀareꢀeffectivelyꢀexecutedꢀinꢀoneꢀcycle,ꢀwithꢀtheꢀ
exceptionꢀofꢀbranchꢀorꢀcallꢀinstructions.ꢀAnꢀ8-bitꢀwideꢀALUꢀisꢀusedꢀinꢀpracticallyꢀallꢀoperationsꢀ
ofꢀtheꢀinstructionꢀset.ꢀItꢀcarriesꢀoutꢀarithmeticꢀoperations,ꢀlogicꢀoperations,ꢀrotation,ꢀincrement,ꢀ
decrement,ꢀbranchꢀdecisions,ꢀetc.ꢀTheꢀinternalꢀdataꢀpathꢀisꢀsimplifiedꢀbyꢀmovingꢀdataꢀthroughꢀtheꢀ
AccumulatorꢀandꢀtheꢀALU.ꢀCertainꢀinternalꢀregistersꢀareꢀimplementedꢀinꢀtheꢀDataꢀMemoryꢀandꢀ
canꢀbeꢀdirectlyꢀorꢀindirectlyꢀaddressed.ꢀTheꢀsimpleꢀaddressingꢀmethodsꢀofꢀtheseꢀregistersꢀalongꢀ
withꢀadditionalꢀarchitecturalꢀfeaturesꢀensureꢀthatꢀaꢀminimumꢀofꢀexternalꢀcomponentsꢀisꢀrequiredꢀtoꢀ
provideꢀaꢀfunctionalꢀI/OꢀandꢀA/Dꢀsystemꢀwithꢀmaximumꢀreliabilityꢀandꢀflexibility.
Clocking and Pipelining
Theꢀmainꢀsystemꢀclock,ꢀderivedꢀfromꢀHIRCꢀoscillatorꢀisꢀsubdividedꢀintoꢀfourꢀinternallyꢀgeneratedꢀ
non-overlappingꢀclocks,ꢀT1~T4.TheꢀProgramꢀCounterꢀisꢀincrementedꢀatꢀtheꢀbeginningꢀofꢀtheꢀT1ꢀ
clockꢀduringꢀwhichꢀtimeꢀaꢀnewꢀinstructionꢀisꢀfetched.ꢀTheꢀremainingꢀT2~T4ꢀclocksꢀcarryꢀoutꢀtheꢀ
decodingꢀandꢀexecutionꢀfunctions.ꢀInꢀthisꢀway,ꢀoneꢀT1~T4ꢀclockꢀcycleꢀformsꢀoneꢀinstructionꢀcycle.ꢀ
Althoughꢀtheꢀfetchingꢀandꢀexecutionꢀofꢀinstructionsꢀtakesꢀplaceꢀinꢀconsecutiveꢀinstructionꢀcycles,ꢀtheꢀ
pipeliningꢀstructureꢀofꢀtheꢀmicrocontrollerꢀensuresꢀthatꢀinstructionsꢀareꢀeffectivelyꢀexecutedꢀinꢀoneꢀ
instructionꢀcycle.ꢀTheꢀexceptionꢀtoꢀthisꢀareꢀinstructionsꢀwhereꢀtheꢀcontentsꢀofꢀtheꢀProgramꢀCounterꢀ
areꢀchanged,ꢀsuchꢀasꢀsubroutineꢀcallsꢀorꢀjumps,ꢀinꢀwhichꢀcaseꢀtheꢀinstructionꢀwillꢀtakeꢀoneꢀmoreꢀ
instructionꢀcycleꢀtoꢀexecute.
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System Clocking and Pipelining
Forꢀinstructionsꢀinvolvingꢀbranches,ꢀsuchꢀasꢀjumpꢀorꢀcallꢀinstructions,ꢀtwoꢀinstructionꢀcyclesꢀareꢀ
requiredꢀtoꢀcompleteꢀinstructionꢀexecution.ꢀAnꢀextraꢀcycleꢀisꢀrequiredꢀasꢀtheꢀprogramꢀtakesꢀoneꢀ
cycleꢀtoꢀfirstlyꢀobtainꢀtheꢀactualꢀjumpꢀorꢀcallꢀaddressꢀandꢀthenꢀanotherꢀcycleꢀtoꢀactuallyꢀexecuteꢀtheꢀ
branch.ꢀTheꢀrequirementꢀforꢀthisꢀextraꢀcycleꢀshouldꢀbeꢀtakenꢀintoꢀaccountꢀbyꢀprogrammersꢀinꢀtimingꢀ
sensitiveꢀapplications.
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Instruction Fetching
Rev. 1.21
11
April 11, 2017
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
