HT46RU67/HT46CU67
Bit No.
Label
Function
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation, otherwise C is cleared. C is also affected by a ro-
tate through carry instruction.
0
C
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction, otherwise AC is cleared.
1
2
3
AC
Z
Z is set if the result of an arithmetic or logic operation is zero, otherwise Z is cleared.
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa, otherwise OV is cleared.
OV
PDF is cleared by either a system power-up or executing the ²CLR WDT² instruction. PDF is
set by executing the ²HALT² instruction.
4
PDF
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO
5
TO
is set by a WDT time-out.
6, 7
¾
Unused bit, read as ²0²
Status (0AH) Register
Interrupts - INTC0, INTC1, MFIC
on pins INT0
or INT1 . A configuration option exists to
select one of three transition types, either high to low,
low to high or both. The related interrupt request flag,
EIF0; bit 4 of the INTC0 register and EIF1; bit 5 of the
INTC0 register, will be set when an external interrupt oc-
curs. After the interrupt is enabled, the stack is not full,
and the external interrupt is active, a subroutine call to
location 04H or 08H occurs. The interrupt request flag,
EIF0 or EIF1 and the EMI bits are all cleared to disable
other maskable interrupts.
The device provides two external interrupts, an A/D con-
verter interrupt, two Internal Timer/Event Counter (0/1)
interrupts, a UART Bus interrupt, SIO (Serial interface)
interrupt, and a Multi-function interrupt. The Multi-func-
tion interrupt includes the internal Timer/Event Counter
2 interrupt, the internal real time clock interrupt, and the
internal time base interrupt . The Interrupt Control regis-
ter 0, INTC0;0BH, interrupt control register 1,
INTC1;1EH, and the Multi-Function interrupt control
register, MFIC;2FH, contain the interrupt control bits
that are used to set the enable/disable status and inter-
rupt request flags.
The 04H vector, in addition to existing for the INT0 ex-
ternal interrupt, is also shared with the A/D converter in-
terrupt. The interrupt selection for this vector is chosen
via configuration option. If the A/D converter interrupt is
chosen, then any trigger edge on pin INT0 will not gen-
erate an interrupt. In this case, when an A/D conversion
process has completed, if the EMI and EADI bits are en-
abled and, the stack is not full, a subroutine call to loca-
tion 04H will occur.
Once an interrupt subroutine is serviced, other inter-
rupts are all blocked automatically as the EMI bit is
cleared. This scheme may prevent any further interrupt
nesting. Other interrupt requests may take place during
this interval, but only the interrupt request flag will be re-
corded. If a certain interrupt requires servicing within the
service routine, the EMI bit and the corresponding bits in
the INTC0, INTC1 and MFIC registers may be set in or-
der to allow interrupt nesting. Once the stack is full, the
interrupt request will not be acknowledged, even if the
related interrupt is enabled, until the SP is decremented.
If immediate service is desired, the stack should be pre-
vented from becoming full.
The internal Timer/Event Counter 0 interrupt is initial-
ised by setting the Timer/Event Counter 0 interrupt re-
quest flag, T0F; bit 6 of the INTC0 register, which is
normally caused by a timer overflow. After the interrupt
is enabled, and the stack is not full, and the T0F bit is
set, a subroutine call to location 0CH occurs. The re-
lated interrupt request flag, T0F, is reset, and the EMI bit
is cleared to disable other maskable interrupts.
All these interrupts can support a wake-up function. As
an interrupt is serviced, a control transfer occurs by
pushing the contents of the program counter onto the
stack followed by a branch to a subroutine at the speci-
fied location in the Program Memory. Only the contents
of the program counter is pushed onto the stack. If the
contents of the register or the status register is altered
by the interrupt service program which corrupts the de-
sired control sequence, the contents should be saved in
advance.
The Timer/Event Counter 1 and Timer/Event Counter 2
operates in the same manner, The Timer/Event Counter
1 related interrupt request flag is T1F, bit 4 of the INTC1
register, and its subroutine call location is 010H. The
Timer/Event Counter 2 related interrupt request flags
are MFF, bit 6 of the INTC1 register, and T2F, bit 4 of the
MFIC register, and its subroutine call location is 018H.
The related interrupt request flags, T1F and MFF, will be
reset and the EMI bit cleared to disable further inter-
rupts. T2F, bit 4 of the MFIC register, will not be cleared
automatically, and should be cleared by the user.
External interrupts are triggered by an edge transition
Rev. 1.10
12
May 27, 2010
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
