HT46RU25/HT46CU25
0
0
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
8
9
H
H
H
H
H
H
H
H
H
H
I
n
d
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r
e
c
t
A
d
d
r
e
M
e
M
s
s
i
n
g
R
e
g
i
s
t
e
r
0
·
·
Increment and Decrement (INC, DEC)
Branch decision (SZ, SNZ, SIZ, SDZ)
P
0
I
n
d
i
r
e
c
t
A
d
d
r
s
s
i
n
g
R
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r
1
The ALU not only saves the results of a data operation
but also changes the status register.
P
1
B
P
A
C
C
Status Register - STATUS
P
C
L
T
B
L
P
The status register (0AH) is 8 bits wide and contains, a
carry flag (C), an auxiliary carry flag (AC), a zero flag (Z),
an overflow flag (OV), a power down flag (PDF), and a
Watchdog time-out flag (TO). It also records the status in-
formation and controls the operation sequence. Except
for the TO and PDF flags, bits in the status register can be
altered by instructions similar to other registers. Data
written into the status register does not alter the TO or
PDF flags. Operations related to the status register, how-
ever, may yield different results from those intended. The
TO and PDF flags can only be changed by a Watchdog
Timer overflow, chip power-up, or clearing the Watchdog
Timer and executing the ²HALT² instruction.
T
B
L
H
R
T
C
C
0
0
A
B
H
H
S
T
A
T
U
S
I
N
T
C
0
0
0
C
D
H
H
T
M
R
0
H
T
M
R
0
L
0
E
H
H
T
T
M
M
R
R
0
1
C
H
0
F
1
1
1
1
1
1
1
1
1
1
0
1
2
3
4
5
6
7
8
9
H
H
H
H
H
H
H
H
H
H
T
M
R
1
L
T
M
R
1
C
P
A
P
A
C
P
B
P
B
C
The Z, OV, AC, and C flags reflect the status of the latest
operations. On entering the interrupt sequence or exe-
cuting the subroutine call, the status register will not be
automatically pushed onto the stack. If the contents of
the status is important, and if the subroutine is likely to
corrupt the status register, the programmer should take
precautions and save it properly.
P
C
P
C
C
P
D
P
D
C
S
p
e
c
i
a
l
P
u
r
p
o
s
e
1
1
A
B
H
H
P
P
P
P
W
W
W
W
M
M
M
M
0
1
2
3
D
a
t
a
M
e
m
o
r
y
1
1
C
D
H
H
1
E
H
H
Interrupts - INTC0, INTC1, MFIC
I
N
T
C
1
1
F
T
B
H
P
The device provides one external interrupt, two internal
timer/event counter 0/1 interrupts, UART Bus interrupt,
I2C-Bus interrupt, the Multi-function interrupt
(timer/event counter 2 interrupt, real time clock interrupt,
time base interrupt), The interrupt control register 0
(INTC0;0BH), interrupt control register 1 (INTC1;1EH)
and Multi-Function interrupt control register (MFIC;2FH)
contains the interrupt control bits to set the enable/dis-
able and the interrupt request flags.
2
2
2
2
2
2
2
2
2
2
0
1
2
3
4
5
6
7
8
9
H
H
H
H
H
H
H
H
H
H
H
A
D
R
H
C
R
H
S
R
H
D
R
A
D
R
L
A
A
D
D
R
C
H
R
A
C
S
R
P
F
P
F
C
Once an interrupt subroutine is serviced, all the other in-
terrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain inter-
rupt requires servicing within the service routine, the
EMI bit and the corresponding bit of the INTC0, INTC1
and MFIC may be set to allow interrupt nesting. If the
stack is full, the interrupt request will not be acknowl-
edged, even if the related interrupt is enabled, until the
SP is decremented. If immediate service is desired, the
stack must be prevented from becoming full.
2
2
A
B
H
H
P
G
P
G
C
2
2
C
D
H
H
T
M
R
2
2
E
H
H
T
M
R
2
C
2
F
M
F
I
C
3
3
3
3
0
1
2
3
H
H
H
H
H
U
S
R
U
U
C
C
R
R
1
2
T
X
R
/
R
X
R
3
3
4
5
B
R
G
H
3
F
H
H
All these kinds of interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
a branch to a subroutine at specified location in the pro-
gram memory. Only the program counter is pushed onto
the stack. If the contents of the register or status register
4
0
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:
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3
B
a
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:
B
a
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k
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,
B
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1
,
B
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2
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R
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0
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F
F
H
RAM Mapping
Rev. 1.30
10
March 9, 2007
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
