HT46R63/HT46C63
Pad Assignment
HT46C63
C H G O
C M P O
C M P N
C M P P
C O M 0
O S C 3
O S C 4
O S C 1
O S C 2
V L C D
V D D
R E S
7 2
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
P A 0
P A 1
P A 2
P A 3
P A 4
P A 5
P A 6
P A 7
V S S
V S S
A N 0 /P B 0
A N 1 /P B 1
A N 2 /P B 2
A N 3 /P B 3
A N 4 /P B 4
A N 5 /P B 5
A N 6 /P B 6
A N 7 /P B 7
6 9
7 1
7 0
6 8
6 7
6 6
6 4
6 5
6 2
6 3
6 0
6 1
5 9
5 8
5 7
5 6
5 5
5 4
5 3
5 2
5 1
5 0
4 9
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
3 8
C O M 1
C O M 2
C O M 3 /S E G 1 9
S E G 1 8
S E G 1 7
S E G 1 6
S E G 1 5
S E G 1 4
S E G 1 3
S E G 1 2
S E G 1 1
S E G 1 0
S E G 9
S E G 8
S E G 7
S E G 6
S E G 5
S E G 4
S E G 3
S E G 2
S E G 1
T R IM 3
T R IM 2
T R IM 1
(0 , 0 )
1 9
2 0
P C 0
2 1
P C 1
2 2
P C 2
2 3
P C 3
2 4
P C 4
2 5
P C 5
2 6
P C 6
2 7
P C 7
2 8
P D 0 /P W M 0
2 9
P D 1 /P W M 1
3 0
P D 2 /P W M 2
3 1
P D 3 /P W M 3
3 2
P D 4 /IN T 0
3 3
P D 5 /IN T 1
3 4
P D 6 /T M R
3 5
P D 7
3 6
3 7
S E G 0
* The IC substrate should be connected to VSS in the PCB layout artwork.
A V D D
Pin Description
Pin Name
PA0~PA7
I/O
I/O
Option
Pull-high
Wake-up
Description
I/O lines with pull-high resistors (bit option). I/O modes of each line are con-
trolled by related control register bit (PAC). Each line of PA can be optioned
as a wake-up input (bit option). I/O configurations: Schmitt trigger/CMOS
I/O lines with pull-high resistors (bit option). I/O modes of each line are con-
trolled by related control register bit (PBC). I/O configurations: Schmitt trig-
ger/CMOS. Each PB line is pin shared with an A/D converter input.
I/O lines with pull-high resistors (bit option). I/O modes of each line are con-
trolled by related control register bit (PCC). I/O configurations: Schmitt trig-
ger/CMOS.
PB0/AN0~
PB7/AN7
PC0~PC6,
PC7
PD0/PWM0~
PD3/PWM3,
PD4/INT0,
PD5/INT1,
PD6/TMR,
PD7
I/O
Pull-High
I/O
Pull-High
I/O
I/O lines with pull-high resistors (bit option). I/O modes of each line are con-
Pull-High PWM
trolled by related control register bit (PDC). I/O configurations: Schmitt trig-
Interrupt Falling
ger/CMOS. The PD0~PD3 can be selected as PWM outputs. INT0/INT1
and/or Rising
are falling/rising edge selectable triggers.
Rev. 1.90
4
May 17, 2004
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
