欢迎访问ic37.com |
会员登录 免费注册
发布采购

HT46C63(56SSOP-A) 参数 Datasheet PDF下载

HT46C63(56SSOP-A)图片预览
型号: HT46C63(56SSOP-A)
PDF下载: 下载PDF文件 查看货源
内容描述: [Microcontroller, 8-Bit, UVPROM, 8MHz, CMOS, PDSO56]
分类和应用: 可编程只读存储器LTE微控制器光电二极管
文件页数/大小: 43 页 / 311 K
品牌: HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
 浏览型号HT46C63(56SSOP-A)的Datasheet PDF文件第2页浏览型号HT46C63(56SSOP-A)的Datasheet PDF文件第3页浏览型号HT46C63(56SSOP-A)的Datasheet PDF文件第4页浏览型号HT46C63(56SSOP-A)的Datasheet PDF文件第5页浏览型号HT46C63(56SSOP-A)的Datasheet PDF文件第7页浏览型号HT46C63(56SSOP-A)的Datasheet PDF文件第8页浏览型号HT46C63(56SSOP-A)的Datasheet PDF文件第9页浏览型号HT46C63(56SSOP-A)的Datasheet PDF文件第10页  
HT46R63/HT46C63  
Test Conditions  
Conditions  
¾
Symbol  
IOLTOTAL  
RPH  
Parameter  
Min.  
Typ.  
Max.  
Unit  
mA  
kW  
VDD  
¾
I/O Port Total Sink Current  
Pull-High Resistance (I/O)  
Comparator Input Offset Voltage  
100  
100  
50  
¾
20  
¾
60  
30  
¾
3V  
5V  
¾
¾
10  
VOS  
VI  
10  
mV  
V
¾
¾
¾
¾
-10  
Comparator Input Voltage  
Range  
VDD-0.8  
VDD  
0.2  
0
¾
¾
¾
¾
¾
VAD  
EAD  
A/D Input Voltage  
V
A/D Conversion Integral  
Nonlinearity Error  
LSB  
¾
±0.5  
±1  
3V  
5V  
0.5  
1.5  
1
3
mA  
mA  
¾
¾
Additional Power Consumption  
if A/D Converter is Used  
IADC  
¾
Note:  
²*fS² please refer to clock option of Watchdog Timer  
A.C. Characteristics  
Ta=25°C  
Test Conditions  
Conditions  
Symbol  
Parameter  
Min.  
Typ.  
Max.  
Unit  
VDD  
¾
2.2V~5.5V  
400  
400  
4000  
8000  
¾
¾
fSYS1  
fSYS2  
fTIMER  
System Clock (Crystal)  
kHz  
Hz  
3.3V~5.5V  
2.2V~5.5V  
¾
System Clock  
32768  
¾
¾
¾
(32768Hz Crystal OSC)  
2.2V~5.5V  
3.3V~5.5V  
0
0
4000  
8000  
180  
¾
¾
¾
¾
90  
65  
Timer Input Frequency  
kHz  
3V  
5V  
45  
32  
tWDTOSC  
Watchdog Oscillator Period  
¾
ms  
130  
Watchdog Time-out Period  
(WDT OSC)  
216  
218  
tWDTOSC  
¾
¾
¾
¾
¾
¾
¾
¾
Watchdog Time-out Period  
( fSYS/4)  
tWDT  
tSYS  
Watchdog Time-out Period  
(32768Hz)  
216  
¾
tRTCOSC  
¾
¾
¾
¾
¾
¾
1
¾
¾
¾
tRES  
tSST  
External Reset Low Pulse Width  
System Start-up Timer Period  
ms  
Power-up or wake-up  
from HALT  
tSYS  
1024  
¾
tINT  
Interrupt Pulse Width  
A/D Clock Period  
1
1
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
32  
¾
¾
¾
¾
¾
3
ms  
ms  
tAD  
tADC  
tADCS  
tCOMP  
tAD  
tAD  
A/D Conversion Time  
A/D Sampling Time  
64  
¾
¾
Response Time of Comparator  
ms  
Note: tSYS=1/fSYS1 or 1/fSYS2  
Rev. 2.30  
6
March 22, 2006