HT46R63/HT46C63
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vated level is indexed by the stack pointer and is not ac-
cessible. At subroutine call or interrupt
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1
acknowledgment, the contents of the program counter
are pushed onto the stack. At the end of a subroutine or
an interrupt routine, signaled by a return instruction
(RET or RETI), the program counter is restored to its
previous value from the stack. After a chip reset, the
stack pointer will point to the top of the stack.
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1
B
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A
C
C
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L
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B
L
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L
H
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C
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledgment will be inhibited. When the stack
pointer is decreased (by RET or RETI), the interrupt will
be serviced. This feature prevents stack overflow allow-
ing the programmer to use the structure more easily. In
similar case, if the stack is full and a ²call² is subse-
quently executed, stack overflow occurs and the first en-
try will be lost (only the most recent 8 return addresses
are stored).
0
0
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B
H
H
S
T
A
T
U
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N
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C
0
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1
1
1
1
1
1
1
1
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1
0
1
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9
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Data Memory - RAM
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The data memory is designed with 239´8 bits. The
data memory is divided into two functional groups: spe-
cial function registers and general purpose data mem-
ory (208´8). Most are read/write, but some are read
only.
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1
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M
M
0
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3
1
1
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D
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H
The special function registers include the indirect ad-
dressing register 0 and 1 (R0;00H, R1;02H), memory
pointer 0 and 1 (MP0;01H, MP1;03H), bank pointer
(BP:04H), accumulator (ACC;05H), program counter
lower-order byte register (PCL;06H), table pointer
(TBLP;07H), table higher-order byte register
(TBLH;08H), real time clock control register
(RTCC;09H), status register (STATUS;0AH), interrupt
control register (INTC0;0BH), timer higher-order byte
register (TMRH;0CH), timer lower-order byte register
(TMRL;0DH), timer control register (TMRC;0EH), I/O
port data registers (PA;12H, PB;14H, PC;16H, PD;18H),
I/O port control registers (PAC;13H, PBC;15H,
PCC;17H, PDC;19H), PWM0 (1AH), PWM1 (1BH),
PWM2 (1CH), PWM3 (1DH), INTC1 (1EH),the A/D re-
sult register (ADR;21H), the A/D control register
(ADCR;22H) and the A/D clock setting register
(ACSR;23H). The remaining space before the 30H is re-
served for future expansion and reading these locations
will return the result ²00H². The general-purpose data
memory, addressed from 30H to FFH, is used for data
and control information under instruction commands.
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RAM Mapping
Indirect Addressing Register
Location 00H (02H) is indirect addressing registers that
are not physically implemented. Any read/write opera-
tion of [00H] ([02H]) will access data memory pointed to
by MP0 (MP1). Reading location 00H (02H) itself indi-
rectly will return the result ²00H². Writing indirectly re-
sults in no operation.
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations di-
rectly. Except for some dedicated bits, each bit in the
data memory can be set and cleared by ²SET [m].i² and
²CLR [m].i², respectively. They are also indirectly acces-
sible through memory pointers (MP0 and MP1).
The memory pointers are 8-bit registers. Only the
MP1/R1 can be used to access the LCD RAM (BP=1).
Rev. 2.30
9
March 22, 2006
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
