HT46R62/HT46C62
Stack Register - STACK
decrement and rotate operations directly. Except for
some dedicated bits, each bit in the data memory can be
set and reset by ²SET [m].i² and ²CLR [m].i². They are
also indirectly accessible through memory pointer regis-
ters (MP0;01H/MP1;03H). The space before 28H is
overlapping in each bank.
The stack register is a special part of the memory used
to save the contents of the program counter. The stack
is organized into 6 levels and is neither part of the data
nor part of the program, and is neither readable nor
writeable. Its activated level is indexed by a stack
pointer (SP) and is neither readable nor writeable. At the
start of a subroutine call or an interrupt acknowledg-
ment, the contents of the program counter is pushed
onto the stack. At the end of the subroutine or interrupt
routine, signaled by a return instruction (RET or RETI),
the contents of the program counter is restored to its
previous value from the stack. After chip reset, the SP
will point to the top of the stack.
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If the stack is full and a non-masked interrupt takes
place, the interrupt request flag is recorded but the ac-
knowledgment is still inhibited. Once the SP is decre-
mented (by RET or RETI), the interrupt is serviced. This
feature prevents stack overflow, allowing the program-
mer to use the structure easily. Likewise, if the stack is
full, and a ²CALL² is subsequently executed, a stack
overflow occurs and the first entry is lost (only the most
recent sixteen return addresses are stored).
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Data Memory - RAM
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The data memory (RAM) is designed with 116´8 bits,
and is divided into two functional groups, namely; spe-
cial function registers 28´8 bit and general purpose data
memory, 88´8 bit most of which are readable/writable,
although some are read only. The special function regis-
ter are overlapped in any banks.
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Of the two types of functional groups, the special func-
tion registers consist of an Indirect addressing register 0
(00H), a Memory pointer register 0 (MP0;01H), an Indi-
rect addressing register 1 (02H), a Memory pointer reg-
ister 1 (MP1;03H), a Bank pointer (BP;04H), an
Accumulator (ACC;05H), a Program counter
lower-order byte register (PCL;06H), a Table pointer
(TBLP;07H), a Table higher-order byte register
(TBLH;08H), a Real time clock control register
(RTCC;09H), a Status register (STATUS;0AH), an Inter-
rupt control register 0 (INTC0;0BH), Interrupt control
register 1 (INTC1;1EH) , PWM data register
(PWM0;1AH, PWM1;1BH, PWM2;1CH), the A/D result
lower-order byte register (ADRL;24H), the A/D result
higher-order byte register (ADRH;25H), the A/D control
register (ADCR;26H), the A/D clock setting register
(ACSR;27H), I/O registers (PA;12H, PB;14H, PD;18H)
and I/O control registers (PAC;13H, PBC;15H,
PDC;19H). The space before 28H is overlapping in each
bank. The general purpose data memory, addressed
from 28H to 7FH, is used for data and control informa-
tion under instruction commands. All of the data mem-
ory areas can handle arithmetic, logic, increment,
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RAM Mapping
Rev. 1.70
9
February 14, 2006
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
