HT46R46E/C46E/R47E/C47E/R48AE/C48AE/R49E
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
¾
Conditions
tRES
tSST
tLVR
tINT
External Reset Low Pulse Width
System Start-up Timer Period
Low Voltage Reset Time
Interrupt Pulse Width
1
¾
¾
¾
1024
1
¾
¾
2
ms
*tSYS
Wake-up from HALT
¾
0.25
1
ms
¾
¾
¾
¾
¾
¾
ms
A/D Clock Period -
tAD1
0.5
1
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
64
76
32
32
¾
¾
¾
¾
¾
¾
ms
HT46R46E
A/D Clock Period -
tAD2
ms
HT46R47E/HT46R48AE/HT46R49E
A/D Conversion Time -
tADC1
tADC2
tADCS1
tADCS2
tAD1
tAD2
tAD1
tAD2
¾
¾
¾
¾
HT46R46E
A/D Conversion Time -
HT46R47E/HT46R48AE/HT46R49E
A/D Sampling Time -
HT46R46E
A/D Sampling Time -
HT46R47E/HT46R48AE/HT46R49E
Note: *tSYS=1/fSYS
Ta=25°C
EEPROM - A.C. Characteristics
Standard
Mode*
V
CC=5V±10%
Symbol
Parameter
Remark
Unit
Min.
Max.
Min.
Max.
400
¾
fSK
Clock Frequency
100
¾
kHz
ns
¾
¾
¾
600
1200
¾
tHIGH
tLOW
tr
Clock High Time
4000
4700
¾
¾
¾
Clock Low Time
ns
¾
¾
SDA and SCL Rise Time
SDA and SCL Fall Time
Note
Note
1000
300
300
300
ns
tf
ns
¾
¾
After this period the
first clock pulse is
generated
tHD:STA
START Condition Hold Time
START Condition Setup Time
4000
4000
600
600
ns
ns
¾
¾
¾
¾
Only relevant for
repeated START
condition
tSU:STA
tHD:DAT
tSU:DAT
tSU:STO
tAA
Data Input Hold Time
0
0
ns
ns
ns
ns
¾
¾
¾
¾
¾
Data Input Setup Time
STOP Condition Setup Time
Output Valid from Clock
200
4000
¾
100
600
¾
¾
¾
¾
¾
3500
900
¾
Time in which the bus
tBUF
Bus Free Time
must be free before a new 4700
transmission can start
1200
ns
¾
¾
Input Filter Time Constant
(SDA and SCL Pins)
tSP
Noise suppression time
100
5
50
5
ns
¾
¾
¾
¾
tWR
Write Cycle Time
ms
¾
Note: These parameters are periodically sampled but not 100% tested
* The standard mode means VCC=2.2V to 5.5V
Rev. 1.31
7
December 29, 2008
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
