HT46R232/HT46C232
All these kinds of interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
a branch to a subroutine at specified location in the pro-
gram memory. Only the program counter is pushed onto
the stack. If the contents of the register or status register
(STATUS) are altered by the interrupt service program
which corrupts the desired control sequence, the con-
tents should be saved in advance.
The A/D converter interrupt is initialized by setting the
A/D converter request flag (ADF; bit 4 of INTC1),
caused by an end of A/D conversion. When the interrupt
is enabled, the stack is not full and the ADF is set, a sub-
routine call to location 10H will occur. The related inter-
rupt request flag (ADF) will be reset and the EMI bit
cleared to disable further interrupts.
The I2C Bus interrupt is initialized by setting the I2C Bus in-
terrupt request flag (HIF; bit 5 of INTC1), caused by a
slave address match (HAAS=²1²) or one byte of data
transfer is completed. When the interrupt is enabled, the
stack is not full and the HIF bit is set, a subroutine call to
location 14H will occur. The related interrupt request flag
(HIF) will be reset and the EMI bit cleared to disable further
interrupts.
External interrupts are triggered by a high to low transi-
tion of INT and the related interrupt request flag (EIF; bit
4 of INTC0) will be set. When the interrupt is enabled,
the stack is not full and the external interrupt is active, a
subroutine call to location 04H will occur. The interrupt
request flag (EIF) and EMI bits will be cleared to disable
other interrupts.
During the execution of an interrupt subroutine, other in-
terrupt acknowledgments are held until the ²RETI² in-
struction is executed or the EMI bit and the related
interrupt control bit are set to 1 (of course, if the stack is
not full). To return from the interrupt subroutine, ²RET² or
²RETI² may be invoked. RETI will set the EMI bit to en-
able an interrupt service, but RET will not.
The internal Timer/Event Counter 0 interrupt is initial-
ized by setting the Timer/Event Counter 0 interrupt re-
quest flag (T0F; bit 5 of INTC0), which is normally
caused by a timer overflow. After the interrupt is en-
abled, and the stack is not full, and the T0F bit is set, a
subroutine call to location 08H occurs. The related inter-
rupt request flag (T0F) is reset, and the EMI bit is
cleared to disable further maskable interrupts. The
Timer/Event Counter 1 is operated in the same manner
but its related interrupt request flag is T1F (bit 6 of
INTC0) and its subroutine call location is 0CH.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
Bit No.
Label
EMI
EEI
Function
0
1
2
3
4
5
6
Controls the master (global) interrupt (1= enabled; 0= disabled)
Controls the external interrupt (1= enabled; 0= disabled)
ET0I
ET1I
EIF
Controls the Timer/Event Counter 0 interrupt (1= enabled; 0= disabled)
Controls the Timer/Event Counter 1 interrupt (1= enabled; 0= disabled)
External interrupt request flag (1= active; 0= inactive)
T0F
T1F
Internal Timer/Event Counter 0 request flag (1= active; 0= inactive)
Internal Timer/Event Counter 1 request flag (1= active; 0= inactive)
For test mode used only.
7
¾
Must be written as ²0²; otherwise may result in unpredictable operation.
INTC0 (0BH) Register
Bit No.
Label
EADI
EHI
¾
Function
Control the A/D converter interrupt (1= enabled; 0=disabled)
Control the I2C Bus interrupt (1= enabled; 0= disabled)
Unused bit, read as ²0²
0
1
2, 3
4
ADF
HIF
¾
A/D converter request flag (1= active; 0= inactive)
I2C Bus interrupt request flag (1= active; 0= inactive)
Unused bit, read as ²0²
5
6, 7
INTC1 (1EH) Register
Rev. 1.50
10
January 21, 2009
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
