HT46R232/HT46C232
Functional Description
Execution Flow
The system clock is derived from either a crystal or an
RC oscillator. It is internally divided into four
non-overlapping clocks. One instruction cycle consists
of four system clock cycles. Instruction fetching and ex-
ecution are pipelined in such a way that a fetch takes
one instruction cycle while decoding and execution
takes the next instruction cycle. The pipelining scheme
makes it possible for each instruction to be effectively
executed in a cycle. If an instruction changes the value
of the program counter, two cycles are required to com-
plete the instruction.
Program Counter
-
PC
The program counter (PC) is 12 bits wide and it controls
the sequence in which the instructions stored in the pro-
gram ROM are executed. The contents of the PC can
specify a maximum of 4096 addresses. After accessing
a program memory word to fetch an instruction code,
the value of the PC is incremented by 1. The PC then
points to the memory word containing the next instruc-
tion code. When executing a jump instruction, condi-
tional skip execution, loading a PCL register, a
subroutine call, an initial reset, an internal interrupt, an
external interrupt, or returning from a subroutine, the PC
manipulates the program transfer by loading the ad-
dress corresponding to each instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get a proper instruction; oth-
erwise proceed to the next instruction.
The lower byte of the PC (PCL) is a readable and
writeable register (06H). Moving data into the PCL per-
forms a short jump. The destination is within 256 loca-
tions.
When a control transfer takes place, an additional
dummy cycle is required.
T 2
T 3
T 4
T 1
T 2
T 3
T 4
S y s te m
O S C 2 (R C
C lo c k
o n ly )
P C
T 1
T 2
T 3
T 4
T 1
P C
P C + 1
P C + 2
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Mode
Initial Reset
External Interrupt
Timer/Event Counter 0 Overflow
Timer/Event Counter 1 Overflow
A/D Converter Interrupt
I
2
C Bus Interrupt
Skip
Loading PCL
Jump, Call Branch
Return from Subroutine
Program Counter
*11
0
0
0
0
0
0
*11
#11
S11
*10
0
0
0
0
0
0
*10
#10
S10
*9
0
0
0
0
0
0
*9
#9
S9
*8
0
0
0
0
0
0
*8
#8
S8
*7
0
0
0
0
0
0
@7
#7
S7
*6
0
0
0
0
0
0
@6
#6
S6
*5
0
0
0
0
0
0
@5
#5
S5
*4
0
0
0
0
1
1
@4
#4
S4
*3
0
0
1
1
0
0
@3
#3
S3
*2
0
1
0
1
0
1
@2
#2
S2
*1
0
0
0
0
0
0
@1
#1
S1
*0
0
0
0
0
0
0
@0
#0
S0
Program Counter + 2
Program Counter
Note:
*11~*0: Program counter bits
#11~#0: Instruction code bits
S11~S0: Stack register bits
@7~@0: PCL bits
Rev. 1.50
6
January 21, 2009
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
