HT45R06
Stack Register
-
STACK
This is a special part of the memory which is used to
save the contents of the program counter only. The
stack is organized into 4 levels and is neither part of the
data nor part of the program space, and is neither read-
able nor writable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
At a subroutine call or interrupt acknowledgment, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction (RET or RETI), the pro-
gram counter is restored to its previous value from the
stack. After a chip reset, the SP will point to the top of the
stack.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledge will be inhibited. When the stack pointer is
decremented (by RET or RETI), the interrupt will be ser-
viced. This feature prevents stack overflow allowing the
programmer to use the structure more easily. In a similar
case, if the stack is full and a
²CALL²
is subsequently
executed, stack overflow occurs and the first entry will
be lost (only the most recent 4 return addresses are
stored).
Data Memory
-
RAM
The data memory is designed with 85´8 bits. The data
memory is divided into 2 functional groups: special func-
tion registers and general purpose data memory (64´8).
Most of them are read/write, but some are read only.
The special function registers include the indirect ad-
dressing register (00H), program counter lower-order
byte register (PCL;06H), memory pointer register
(MP;01H), accumulator (ACC;05H), table pointer
(TBLP;07H), table higher-order byte register
(TBLH;08H), system quick start-up (OSCC;09H) status
register (STATUS;0AH), interrupt control register (INTC;
0BH), a Timer/Event Counter register (TMR;0DH), a
Timer/Event Counter control register (TMRC;0EH), I/O
port data registers (PA;12H, PB;14H, PD;18H), I/O port
control registers (PAC;13H, PBC;15H, PDC;19H), A/D
result register (ADR;21H), A/D control register
( A D C R ; 22H ) and A / D c l o c k s e tt in g r e g is te r
(ACSR;23H). The remaining space before the 40H is re-
served for future expansion and reading these locations
will return the result
²00H².
The general purpose data
memory, addressed from 40H to 7FH, is used for data
and control information under instruction commands.
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations di-
rectly. Except for some dedicated bits, each bit in the
data memory can be set and reset by
²SET
[m].i² and
²CLR
[m].i². They are also indirectly accessible through
memory pointer register (MP;01H).
0 0 H
0 1 H
0 2 H
0 3 H
0 4 H
0 5 H
0 6 H
0 7 H
0 8 H
0 9 H
0 A H
0 B H
0 C H
0 D H
0 E H
0 F H
1 0 H
1 1 H
1 2 H
1 3 H
1 4 H
1 5 H
1 6 H
1 7 H
1 8 H
1 9 H
1 A H
1 B H
1 C H
1 D H
1 E H
1 F H
2 0 H
2 1 H
2 2 H
2 3 H
2 4 H
3 F H
4 0 H
A D R
A D C R
A C S R
P D
P D C
P A
P A C
P B
P B C
S p e c ia l P u r p o s e
D a ta M e m o ry
T M R
T M R C
A C C
P C L
T B L P
T B L H
O S C C
S T A T U S
IN T C
In d ir e c t A d d r e s s in g R e g is te r
M P
In d ir e c t A d d r e s s in g R e g is te r 1
M P 1
G e n e ra l P u rp o s e
D a ta M e m o ry
(6 4 B y te s )
: U n u s e d
R e a d a s "0 0 "
7 F H
RAM Mapping
Indirect Addressing Register
Location 00H is an indirect addressing register that is
not physically implemented. Any read/write operation of
[00H] accesses the data memory pointed to by MP
(01H). Reading location 00H itself indirectly will return
the result 00H. Writing indirectly results in no operation.
The memory pointer register MP (01H) is a 7-bit register.
The bit 7 of MP is undefined and reading will return the
result
²1².
Any writing operation to MP will only transfer
the lower 7-bit data to MP.
Rev. 1.00
8
May 24, 2005
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
