HT36M4
Program ROM
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HT36M4 provides 16 address lines WA15~WA0 to read
the Program ROM which is up to 1M bits, and is com-
monly used for the wavetable voice codes and the pro-
gram memory. It provides two address types, one type is
for program ROM, which is addressed by a bank pointer
PF2~PF0 and a 13-bit program counter PC12~PC0;
and the other type is for wavetable code, which is ad-
dressed by the start address ST0~ST11. On the pro-
gram type, WA15~WA0= PF2~PF0´213+PC12~PC0.
On the wave table ROM type, WA16~WA0=
ST11~ST0´25´8-bit.
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Program Memory - ROM
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The program memory is used to store the program in-
structions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
8192´16 bits, addressed by the bank pointer, program
counter and table pointer.
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Program Memory for Each Bank
·
Table location
Any location in the ROM space can be used as
look-up tables. The instructions ²TABRDC [m]² (the
current page, 1 page=256 words) and ²TABRDL [m]²
(the last page) transfer the contents of the lower-order
byte to the specified data memory, and the
higher-order byte to TBLH (08H). Only the destination
of the lower-order byte in the table is well-defined, the
higher-order byte of the table word are transferred to
the TBLH. The Table Higher-order byte register
(TBLH) is read only. The Table Pointer (TBLP) is a
read/write register (07H), which indicates the table lo-
cation. Before accessing the table, the location must
be placed in the TBLP. The TBLH is read only and
cannot be restored. If the main routine and the ISR
(Interrupt Service Routine) both employ the table read
instruction, the contents of the TBLH in the main rou-
tine are likely to be changed by the table read instruc-
tion used in the ISR. Errors can occur. In this case,
using the table read instruction in the main routine and
the ISR simultaneously should be avoided. However,
if the table read instruction has to be applied in both
the main routine and the ISR, the interrupt should be
disabled prior to the table read instruction. It will not be
enabled until the TBLH has been backed up. All table
related instructions need 2 cycles to complete the op-
eration. These areas may function as normal program
memory depending upon user requirements.
Certain locations in the program memory of each bank
are reserved for special usage:
·
Location 000H on bank0
This area is reserved for the initialization program. Af-
ter chip reset, the program always begins execution at
location 000H on bank0.
·
Location 004H
This area is reserved for the external interrupt service
program. If the INT input pin is activated, the interrupt
is enabled and the stack is not full, the program will
jump to location 004H and begins execution.
·
Location 008H
This area is reserved for the Timer/Event Counter 0 in-
terrupt service program on each bank. If timer interrupt
results from a Timer/Event Counter 0 overflow, and if the
interrupt is enabled and the stack is not full, the program
begins execution at location 008H corresponding to its
bank.
·
Location 00CH
This area is reserved for the Timer/Event Counter 1
interrupt service program on each bank. If a timer in-
terrupt results from a Timer/Event Counter 1 overflow,
and if the interrupt is enabled and the stack is not full,
the program begins execution at location 00CH corre-
sponding to its bank.
Table Location
Instruction (s)
*15~*13
P15~P13 P12 P11 P10 P9
111
*12 *11 *10
*9
*8
P8
1
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
TABRDL [m]
@7 @6 @5 @4 @3 @2 @1 @0
@7 @6 @5 @4 @3 @2 @1 @0
1
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Table Location
Note: *12~*0: Bits of table location
@7~@0: Bits of table pointer
P15~P8: Bits of current Program Counter
Rev. 1.10
6
March 14, 2007
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
