HT36A4
Reset
V
D
D
There are 3 ways in which a reset can occur:
R
E
S
t
S S T
·
RES reset during normal operation
S
S
T
T
i
m
e
-
o
u
t
·
RES reset during HALT
·
WDT time-out reset during normal operation
C
h
i
p
R
e
s
e
t
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re -
set² that just resets the PC and SP, leaving the other cir-
cuits to maintain their state. Some registers remain un-
changed during any other reset conditions. Most
registers are reset to the ²initial condition² when the re-
set conditions are met. By examining the PD and TO
flags, the program can distinguish between different
²chip resets².
Reset timing chart
V
D
D
R
E
S
TO PD
RESET Conditions
RES reset during power-up
RES reset during normal operation
RES wake-up HALT
0
u
0
1
1
0
u
1
u
1
Reset circuit
H
A
L
T
W
a
r
m
R
e
s
e
t
W
T
D
T
e
W
D
T
WDT time-out during normal operation
WDT wake-up HALT
i
m
-
o
u
t
R
e
s
e
t
R
E
S
Note: ²u² stands for unchanged
C
o
l
d
S
S
T
R
e
s
e
t
1
0
-
s
t
a
g
e
To guarantee that the system oscillator has started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses during system
power up or when the system awakes from a HALT
state.
O
S
C
I
R
i
p
p
l
e
C
o
u
n
t
e
r
P
o
w
e
r
-
o
n
D
e
t
e
c
t
i
n
g
Reset configuration
When a system power-up occurs, the SST delay is
added during the reset period. But when the reset co-
mes from the RES pin, the SST delay is disabled. Any
wake-up from HALT will enable the SST delay.
The functional units chip reset status are shown below.
Program counter
Interrupt
000H
Disable
Clear
Prescaler
Clear. After master reset,
WDT begins counting
WDT
Timer Counter (0/1)
Input/output ports
SP
Off
Input mode
Points to the top of stack
Rev. 1.00
12
July 2, 2003
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
