HT36A0
Wavetable ROM
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The ST[15~0] is used to defined the start address of
each sample on the wavetable and read the waveform
data from the location. HT36A0 provides 21 output ad-
dress lines from WA[16~0], the ST[15~0] is used to lo-
cate the major 16 bits i.e. WA[16:5] and the undefined
data from WA[4~0] is always set to 00000b. So the start
address of each sample have to be located at a multiple
of 32. Otherwise, the sample will not be read out cor-
rectly because it has a wrong starting code.
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Stack Register - Stack
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This is a special part of the memory which is used to
save the contents of the program counter (PC) only. The
stack is organized into 8 levels and is neither part of the
data nor part of the program space, and is neither read-
able nor writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
At a subroutine call or interrupt acknowledgment, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction (RET or RETI), the pro-
gram counter is restored to its previous value from the
stack. After a chip reset, the SP will point to the top of the
stack.
S
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0
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F
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledgment will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow al-
lowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a CALL is subse-
quently executed, a stack overflow occurs and the first
entry will be lost (only the most recent eight return ad-
dress are stored).
P
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1
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Data Memory - RAM
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The data memory is designed with 256 ´ 8 bits. The data
memory is divided into three functional groups: special
function registers, wavetable function register, and gen-
eral purpose data memory (208´8). Most of them are
read/write, but some are read only.
2
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The special function registers include the Indirect Ad-
dressing register 0 (00H), the Memory Pointer register 0
(MP0;01H), the Indirect Addressing register 1 (02H), the
Memory Pointer register 1 (MP1;03H), the Accumulator
(ACC;05H), the Program Counter Lower-byte register
(PCL;06H), the Table Pointer (TBLP;07H), the Table
Higher-order byte register (TBLH;08H), the Watchdog
Timer option Setting register (WDTS;09H), the Status
register (STATUS;0AH), the Interrupt Control register
(INTC;0BH), the Timer/event Counter 0 Higher-order
byte register (TMR0H;0CH), the Timer/event Counter 0
Lower-order byte register (TMR0L;0DH), the
Timer/event Counter 0 Control register (TMR0C;0EH),
the Timer/ event Counter 1 Higher-order byte register
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(
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F
F
H
RAM mapping
(TMR1H;0FH), the Timer/event Counter 1 Lower-order
byte register (TMR1L;10H), the Timer/event Counter 1
Control register (TMR1C;11H), the I/O registers
(PA;12H, PB;14H, PC;16H, PD;18H), the program ROM
bank select (PF;1CH)) and the I/O Control registers
(PAC;13H, PBC;15H, PCC;17H, PDC;19H), and the
Rev. 1.20
8
June 18, 2003
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
