32-bit ARM Cortex™-M3 MCU
HT32F1251/51B/52/53
SPI Characteristics
Table 19. SPI Characteristics
Symbol
fSCK
Parameter
SCK clock frequency
SCK clock high time
SCK clock low time
Conditions
Min
—
Typ
—
Max
fPCLK/4
—
Unit
MHz
ns
—
—
—
tSCK(H)
fPCLK/8
fPCLK/8
—
tSCK(L)
—
—
ns
SPI Master mode
tV(MO)
tH(MO)
tSU(MI)
tH(MI)
Data output valid time
—
—
—
—
—
2
—
—
—
—
5
ns
ns
ns
ns
Data output hold time
Data input setup time
Data input hold time
—
—
—
5
5
SPI Slave mode
tSU(SEL)
tH(SEL)
tA(SO)
tDIS(SO)
tV(SO)
tH(SO)
tSU(SI)
tH(SI)
SEL enable setup time
—
—
—
—
—
—
—
—
4 tPCLK
2 tPCLK
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
SEL enable hold time
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data input setup time
Data input hold time
3 tPCLK
10
—
—
25
15
—
5
—
4
—
tSCK
SCK (CPOL = 0)
SCK (CPOL = 1)
tSCK(H)
tSCK(L)
tV(MO)
tH(MO)
MOSI
MISO
DATA VALID
DATA VALID
DATA VALID
DATA VALID
tSU(MI)
tH(MI)
CPHA = 1
DATA VALID
DATA VALID
tH(MO)
tV(MO)
MOSI
MISO
DATA VALID
tSU(MI) tH(MI)
DATA VALID
DATA VALID
DATA VALID
CPHA = 0
DATA VALID
DATA VALID
Figure 7. SPI Timing Diagram – SPI Master Mode
Rev. 1.00
31 of 35
May 27, 2011