32-Bit ARM® Cortex™-M0+ MCU
HT32F52220/HT32F52230
Serial Peripheral Interface – SPI
Supports both master and slave mode
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Frequency of up to (fPCLK/2) MHz for the master mode and (fPCLK/3) MHz for the slave mode
FIFO Depth: 8 levels
Multi-master and multi-slave operation
The Serial Peripheral Interface, SPI, provides an SPI protocol data transmit and receive function
in both master and slave mode. The SPI interface uses 4 pins, which are the serial data input and
output lines MISO and MOSI, the clock line, SCK, and the slave select line, SEL. One SPI device
acts as a master device which controls the data flow using the SEL and SCK signals to indicate the
start of data communication and the data sampling rate. To receive a data byte, the streamed data
bits are latched on a specific clock edge and stored in the data register or in the RX FIFO. Data
transmission is carried out in a similar way but in a reverse sequence. The mode fault detection
provides a capability for multi-master applications.
Universal Synchronous Asynchronous Receiver Transmitter – USART
Supports both asynchronous and clocked synchronous serial communication modes
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Asynchronous operating baud rate up to (fPCLK/16) MHz and synchronous operating rate up to
(fPCLK/8) MHz
Full duplex communication
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Fully programmable serial communication characteristics including:
● Word length: 7, 8, or 9-bit character
● Parity: Even, odd, or no-parity bit generation and detection
● Stop bit: 1 or 2 stop bit generation
● Bit order: LSB-first or MSB-first transfer
Error detection: Parity, overrun and frame error
Auto hardware flow control mode – RTS, CTS
IrDA SIR encoder and decoder
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RS485 mode with output enable control
FIFO Depth: 8 9 bits for both receiver and transmitter
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The Universal Synchronous Asynchronous Receiver Transceiver, USART, provides a flexible full
duplex data exchange using synchronous or asynchronous data transfer. The USART is used to
translate data between parallel and serial interfaces, and is commonly used for RS232 standard
communication. The USART peripheral function supports four types of interrupt including Line
Status Interrupt, Transmitter FIFO Empty Interrupt, Receiver Threshold Level Reaching Interrupt
and Time Out Interrupt. The USART module includes a transmitter FIFO, (TX_FIFO) and receiver
FIFO (RX_FIFO). The software can detect a USART error status by reading the Line Status
Register, LSR. The status includes the type and the condition of transfer operations as well as
several error conditions resulting from Parity, Overrun, Framing and Break events.
Rev. 1.21
12 of 39
April 11, 2017
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
