HT27C010
A.C. Characteristics
Symbol
Read operation
t
ACC
t
CE
t
OE
t
DF
t
OH
Address to Output Delay
Chip Enable to Output Delay
Output Enable to Output Delay
CE or OE High to Output Float, Whichever
Occurred First
Output Hold from Address, CE or OE,
Whichever Occurred First
5V
5V
5V
5V
5V
CE=OE=V
IL
OE=V
IL
CE=V
IL
¾
¾
¾
¾
¾
¾
0
70
70
30
25
¾
ns
ns
ns
ns
ns
Parameter
Test Conditions
V
CC
Conditions
Min.
Typ.
Ta=+25°C±5°C
Max.
Unit
Programming operation
t
AS
t
OES
t
DS
t
AH
t
DH
t
DFP
t
VPS
t
PW
t
VCS
t
CES
t
OE
t
PRT
Address Setup Time
OE Setup Time
Data Setup Time
Address Hold Time
Data Hold Time
Output Enable to Output Float Delay
VPP Setup Time
PGM Program Pulse Width
VCC Setup Time
CE Setup Time
Data Valid from OE
VPP Pulse Rise Time During Programming
6V
6V
6V
6V
6V
6V
6V
6V
6V
6V
6V
6V
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
2
2
2
0
2
0
2
30
2
2
¾
2
¾
¾
¾
¾
¾
¾
¾
75
¾
¾
¾
¾
¾
¾
¾
¾
¾
130
¾
105
¾
¾
150
¾
ms
ms
ms
ms
ms
ns
ms
ms
ms
ms
ns
ms
Test waveforms and measurements
2 .4 V
A C
D r iv in g
L e v e ls
0 .4 5 V
2 .0 V
0 .8 V
A C
Output test load
V
D D
M e a s u re m e n t
L e v e l
1 .3 V
(1 N 9 1 4 )
3 .3 k
9
C
L
t
R
, t
F
< 20ns (10% to 90%)
O u tp u t P in
Note: C
L
=100pF including jig capacitance, except for
the -45 devices, where C
L
=30pF.
Rev. 1.10
4
November 21, 2002
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
