HT27C010
A.C. Characteristics
Ta=+25°C±5°C
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VCC
Conditions
Read Operation
tACC
tCE
CE=OE=VIL
OE=VIL
Address to Output Delay
5V
5V
5V
70
70
30
ns
ns
ns
¾
¾
¾
Chip Enable to Output Delay
Output Enable to Output Delay
tOE
CE=VIL
CE or OE High to Output Float, Whichever
Occurred First
tDF
5V
5V
25
ns
ns
¾
¾
¾
Output Hold from Address, CE or OE,
Whichever Occurred First
tOH
0
¾
Programming Operation
tAS
Address Setup Time
OE Setup Time
6V
6V
6V
6V
6V
6V
6V
6V
6V
6V
6V
6V
2
2
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
75
¾
¾
¾
¾
¾
¾
ms
ms
ms
ms
ms
ns
ms
ms
ms
ms
ns
ms
tOES
tDS
Data Setup Time
2
¾
tAH
Address Hold Time
0
¾
tDH
Data Hold Time
2
¾
tDFP
tVPS
tPW
tVCS
tCES
tOE
Output Enable to Output Float Delay
VPP Setup Time
0
130
¾
2
PGM Program Pulse Width
VCC Setup Time
30
2
105
¾
CE Setup Time
2
¾
Data Valid from OE
150
¾
¾
2
tPRT
VPP Pulse Rise Time During Programming
Test waveforms and Measurements
Output Test Load
2
.
4
V
V
D D
2
.
0
V
A
M
L
C
1
.
3
V
A
C
D
r
i
v
i
n
g
e
a
s
u
r
e
m
e
n
t
L
e
v
e
l
s
e
v
e
l
0
.
8
V
(
1
N
9
1
4
)
0
.
4
5
V
3
.
3
k
tR, tF< 20ns (10% to 90%)
O
u
t
p
u
t
P
i
n
C
L
Note: CL=100pF including jig capacitance, except for
the -45 devices, where CL=30pF.
Rev. 1.20
4
December 5, 2003
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
