HT24LC32
Symbol
Parameter
Remark
Time in which the bus must
be free before a new trans-
mission can start
Noise suppression time
¾
Standard Mode*
Min.
4700
Max.
¾
V
CC
=5V±10%
Min.
1200
Max.
¾
Unit
t
BUF
Bus Free Time
Input Filter Time Constant
(SDA and SCL Pins)
Write Cycle Time
ns
t
SP
t
WR
Note:
¾
¾
100
5
¾
¾
50
5
ns
ms
These parameters are periodically sampled but not 100% tested
* The standard mode means V
CC
=2.4V to 5.5V
For relative timing, refer to timing diagrams
Functional Description
·
Serial clock (SCL)
The SCL input is used for positive edge clock data into
each EEPROM device and negative edge clock data
out of each device.
·
Serial data (SDA)
stable whenever the clock line is high. Changes in
data line while the clock line is high will be interpreted
as a START or STOP condition.
·
Start condition
The SDA pin is bidirectional for serial data transfer.
The pin is open drain driven and may be wired-OR
with any number of other open drain or open collector
devices.
·
A0, A1, A2
A high-to-low transition of SDA with SCL high is a start
condition which must precede any other command
(refer to Start and Stop Definition Timing diagram).
·
Stop condition
The A2, A1 and A0 pins are device address inputs that
are hard wired or left not connected for hardware com-
patibility with HT24LC32. When the pins are hard-
wired, as many as eight 32K devices may be
addressed on a single bus system (device addressing
is discussed in detail under the Device Addressing
section). These inputs must be tied to V
CC
or V
SS
, to
establish the device select code.
·
Write protect (WP)
A low-to-high transition of SDA with SCL high is a stop
condition. After a read sequence, the stop command
will place the EEPROM in a standby power mode (re-
fer to Start and Stop Definition Timing Diagram).
·
Acknowledge
All addresses and data words are serially transmitted
to and from the EEPROM in 8-bit words. The
EEPROM sends a zero to acknowledge that it has re-
ceived each word. This happens during the ninth clock
cycle.
D a ta a llo w e d
to c h a n g e
S D A
The HT24LC32 has a write protect pin that provides
hardware data protection. The write protect pin allows
normal read/write operations when the connection is
grounded. When the write protect pin is connected to
V
CC
, the write protection feature is enabled and oper-
ates as shown in the following table.
WP Pin Status
At V
CC
At V
SS
(floating)
Protect Array
Full array (32K)
Normal read/write operations
S C L
S ta rt
c o n d itio n
A d d re s s o r
a c k n o w le d g e
v a lid
N o A C K
s ta te
S to p
c o n d itio n
Device Addressing
The 32K EEPROM devices require an 8-bit device ad-
dress word following a start condition to enable the chip
for a read or write operation. The device address word
consist of a mandatory one, zero sequence for the first
four most significant bits (refer to the diagram showing
the Device Address). This is common to all the
EEPROM device.
The 32K EEPROM uses the three device address bits
A2, A1, A0 to allow as many as eight devices on the
same bus. These bits must compare to their corre-
sponding hardwired input pins.
Memory Organization
Internally organized with 4096 8-bit words, the 32K re-
quires a 12-bit data word address for random word ad-
dressing.
Device Operations
·
Clock and data transition
Data transfer may be initiated only when the bus is not
busy. During data transfer, the data line must remain
Rev. 1.00
3
March 16, 2006
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
