HT24LC08
Symbol
t
AA
t
BUF
Parameter
Output Valid from Clock
Bus Free Time
Input Filter Time Constant
(SDA and SCL Pins)
Write Cycle Time
Remark
¾
Time in which the bus
must be free before a new
transmission can start
Noise suppression time
¾
Standard Mode*
Min.
¾
4700
Max.
3500
¾
V
CC
=5V±10%
Min.
¾
1200
Max.
900
¾
ns
ns
Unit
t
SP
t
WR
¾
¾
100
5
¾
¾
50
5
ns
ms
Notes: These parameters are periodically sampled but not 100% tested
* The standard mode means V
CC
=2.2V to 5.5V
For relative timing, refer to timing diagrams
Functional Description
·
Serial clock (SCL)
·
Start condition
The SCL input is used for positive edge clock data into
each EEPROM device and negative edge clock data
out of each device.
·
Serial data (SDA)
A high-to-low transition of SDA with SCL high is a start
condition which must precede any other command
(refer to Start and Stop Definition Timing diagram).
·
Stop condition
The SDA pin is bidirectional for serial data transfer.
The pin is open drain driven and may be wired-OR
with any number of other open drain or open collector
devices.
·
A0, A1, A2
A low-to-high transition of SDA with SCL high is a stop
condition. After a read sequence, the stop command
will place the EEPROM in a standby power mode (re-
fer to Start and Stop Definition Timing Diagram).
·
Acknowledge
The HT24LC08 uses the A2 input for hard wire ad-
dressing and a total of two 8K devices may be ad-
dressed on a single bus system. The A0 and A1 pins
have no connection.
·
Write protect (WP)
All addresses and data words are serially transmitted
to and from the EEPROM in 8-bit words. The
EEPROM sends a zero to acknowledge that it has re-
ceived each word. This happens during the ninth clock
cycle.
D a ta a llo w e d
to c h a n g e
S D A
The HT24LC08 has a write protect pin that provides
hardware data protection. The write protect pin allows
normal read/write operations when the connection is
grounded. When the write protect pin is connected to
V
CC
, the write protection feature is enabled and oper-
ates as shown in the following table.
WP Pin Status
At V
CC
At V
SS
Protect Array
Full Array (8K)
Normal Read/Write Operations
S C L
S ta rt
c o n d itio n
A d d re s s o r
a c k n o w le d g e
v a lid
N o A C K
s ta te
S to p
c o n d itio n
Device Addressing
The 8K EEPROM device requires an 8-bit device ad-
dress word following a start condition to enable the chip
for a read or write operation. The device address word
consist of a mandatory one, zero sequence for the first
four most significant bits (refer to the diagram showing
the Device Address). This is common to all the
EEPROM device.
The 8K EEPROM uses the A2 device address bit with
the next two bits for memory page addressing. The A2
bit must compare its corresponding hard-wired input
pin. The A1 and A0 pins have no connection.
Memory Organization
Internally organized with 1024 8-bit words, the 8K re-
quires a 10-bit data word address for random word ad-
dressing.
Device Operations
·
Clock and data transition
Data transfer may be initiated only when the bus is not
busy. During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
data line while the clock line is high will be interpreted
as a START or STOP condition.
Rev. 1.30
3
November 25, 2003
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
