HT24LC08
These page addressing bits on the 8K device should be
considered the most significant bits of the data word ad-
dress which follows. The A0, A1 and A2 pins have no
connection.
The data word address lower four bits are internally in-
cremented following the receipt of each data word.
The higher data word address bits are not incre-
mented, retaining the memory page row location.
The 8th bit device address is the read/write operation
select bit. A read operation is initiated if this bit is high
and a write operation is initiated if this bit is low.
·
Acknowledge polling
To maximize bus throughput, one technique is to allow
the master to poll for an acknowledge signal after the
start condition and the control byte for a write com-
mand have been sent. If the device is still busy imple-
menting its write cycle, then no ACK will be returned.
The master can send the next read/write command
when the ACK signal has finally been received.
If the comparison of the device address succeed the
EEPROM will output a zero at ACK bit. If not, the chip will
return to a standby state.
1
0
1
0
A
2
A
1
A
0
R
/
W
D
e
v
i
c
e
A
d
d
r
e
s
s
S
e
n
d
W
r
i
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C
o
m
m
a
n
d
Write Operations
S
e
n
d
S
t
o
p
C
o
n
d
i
t
i
o
n
·
Byte write
t
o
I
n
i
t
i
a
t
e
W
r
i
t
e
C
y
c
l
e
A write operation requires an 8-bit data word address
following the device address word and acknowledg-
ment. Upon receipt of this address, the EEPROM will
again respond with a zero and then clock in the first
8-bit data word. After receiving the 8-bit data word, the
EEPROM will output a zero and the addressing de-
vice, such as a microcontroller, must terminate the
write sequence with a stop condition. At this time the
EEPROM enters an internally-timed write cycle to the
nonvolatile memory. All inputs are disabled during this
write cycle and EEPROM will not respond until write is
complete (refer to Byte write timing).
S
e
n
d
S
t
a
r
t
S
e
n
d
C
o
n
t
r
o
l
B
y
t
e
w
i
t
h
R
/
W
=
0
N
o
(
A
C
K
=
0
)
?
Y
e
s
N
e
x
t
O
p
e
r
a
t
i
o
n
·
Page write
Acknowledge Polling Flow
Write protect
The 8K EEPROM is capable of a 16-byte page write.
A page write is initiated in the same way as a byte
write, but the microcontroller does not send a stop con-
dition after the first data word is clocked in. Instead, af-
ter the EEPROM acknowledges the receipt of the first
data word, the microcontroller can transmit up to 15
more data words. The EEPROM will respond with a
zero after each data word received. The
microcontroller must terminate the page write se-
quence with a stop condition (refer to Page write timing).
·
The HT24LC08 has a write-protect function and pro-
gramming will then be inhibited when the WP pin is
connected to VCC. Under this mode, the HT24LC08 is
used as a serial ROM.
D
e
v
i
c
e
a
d
d
r
e
s
s
W
o
r
d
a
d
d
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e
s
s
D
A
T
A
S
D
A
S
A
2
A
1
A
0
P
R
/
W
S
t
a
r
t
A
C
K
A
C
K
A
C
K
S
t
o
p
Byte Write Timing
D
e
v
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c
e
a
d
d
r
e
s
s
W
o
r
d
a
d
d
r
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s
s
D
A
T
A
n
D
A
T
A
n
+
1
D
A
T
A
n
+
x
S
P
S
D
A
A
C
K
S
t
a
r
t
A
C
K
A
C
K
A
C
K
S
t
o
p
Page Write Timing
Rev. 1.30
4
November 25, 2003
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
