HT24LC04
A.C. Characteristics
Standard
Mode*
V
=3V±10%
V
=5V±10%
CC
CC
Symbol
Parameter
Remark
Unit
Min.
Max.
100
¾
Min.
¾
Max.
400
¾
Min.
¾
Max.
1000
¾
f
Clock Frequency
¾
¾
¾
¾
4000
4700
¾
kHz
ns
SK
t
t
t
t
Clock High Time
600
1200
¾
400
600
¾
HIGH
Clock Low Time
¾
¾
¾
ns
LOW
SDA and SCL Rise Time
SDA and SCL Fall Time
Note
Note
1000
300
300
300
300
100
ns
r
f
¾
¾
¾
ns
After this period the first
clock pulse is generated
t
t
START Condition Hold Time
START Condition Setup Time
4000
4000
¾
¾
600
600
¾
¾
250
250
¾
¾
ns
ns
HD:STA
SU:STA
Only relevant for repeated
START condition
t
t
t
t
Data Input Hold Time
¾
0
¾
¾
0
¾
¾
¾
¾
¾
ns
ns
ns
ns
HD:DAT
SU:DAT
SU:STO
AA
Data Input Setup Time
STOP Condition Setup Time
Output Valid from Clock
¾
200
4000
¾
100
600
¾
100
250
50
¾
¾
¾
¾
¾
3500
900
550
Time in which the bus must
t
Bus Free Time
be free before a new trans- 4700
mission can start
¾
1200
¾
500
¾
ns
BUF
Input Filter Time Constant
(SDA and SCL Pins)
t
t
Noise suppression time
¾
¾
100
5
¾
¾
50
5
¾
¾
50
5
ns
SP
Write Cycle Time
¾
ms
WR
Note: These parameters are periodically sampled but not 100% tested
* The standard mode means VCC= 2.2V to 5.5V at Ta= -40°C to +85°C
For relative timing, refer to timing diagrams
Functional Description
·
Serial clock (SCL)
VSS. When the write protect pin is connected to Vcc,
The SCL input is used for positive edge clock data into
each EEPROM device and negative edge clock data
out of each device.
the write protection feature is enabled and operates
as shown in the following table.
WP Pin Status
At VCC
Protect Array
Full Array (4K)
Normal Read/Write Operations
·
Serial data (SDA)
The SDA pin is bidirectional for serial data transfer.
The pin is open-drain driven and may be wired-OR
with any number of other open-drain or open collector
devices.
At VSS
Memory Organization
·
HT24LC04, 4K Serial EEPROM
·
A0, A1, A2
Internally organized with 512 8-bit words, random
word addressing requires a 9-bit data word address.
The HT24LC04 uses the A2 and A1 inputs for hard
wire addressing and a total of four 4K devices may be
addressed on a single bus system. The A0 pin is not
connected. (The device addressing is discussed in
detail under the Device Addressing section).
Device Operations
·
Clock and data transition
Data transfer may be initiated only when the bus is not
busy. During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
data line while the clock line is high will be interpreted
as a START or STOP condition.
·
Write protect (WP)
The HT24LC04 has a write protect pin that provides
hardware data protection. The write protect pin allows
normal read/write operations when connected to the
Rev. 1.70
3
June 25, 2010
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
