HT23C040
A.C. Test Condition
V
C C
Output load: see figure right
Input rise and fall time: 10ns
Input pulse levels: 0.4V to 2.4V
Input and output timing reference levels:
0.8V and 2.0V (V
CC
=5V)
1.5V (V
CC
=3V)
O u tp u t
7 7 5
W
1 0 0 p . *
1 2 5 0
W
* In c lu d in g s c o p e a n d jig
Output Load Circuit
Functional Description
The HT23C040 has two modes, namely data read mode
and standby mode, controlled by CE/CE/OE1/OE1 and
OE/OE/NC inputs.
·
Standby mode
·
Data read mode
The HT23C040 offers lower current consumption,
controlled by the chip enable input (CE/CE). When a
low/high level is applied to the CE/CE input regardless
of the output enable (OE/OE/NC) states the chip will
enter the standby mode.
Operation Truth Table
Mode
Read
Deselect
Standby
Note: H=V
IH
, L=V
IL
, X=V
IH
or V
IL
CE/CE
H/L
H/L
L/H
OE/OE
H/L
L/H
X
When both the chip enable (CE/CE/OE1/OE1) and
the output enable (OE/OE/NC) are active, the chip is
in data read mode. Otherwise, active CE/CE and inac-
tive OE/OE/NC result in deselect mode. The output
will remain in Hi-Z state.
A0~A18
Valid
X
X
D0~D7
Data Out
High Z
High Z
Timing Diagrams
Random Read
A d d re s s
A d d re s s
t
A
C E
t
O
E
C E
A d d re s s
t
R
C
A d d re s s
O E
t
A
A
t
O
H
t
H
Z
D A T A
V a lid
V a lid
V a lid
N o te : C E , O E a r e e n a b le
Rev. 1.10
4
December 8, 2003
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
