HT1647
Pad No.
X
Y
Pad No.
X
Y
Pad No.
X
Y
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
1522.60
1654.40
1782.40
1775.70
1775.70
1775.70
1775.70
1775.70
1775.70
1775.70
1775.70
1775.70
1775.70
1775.70
1775.70
1775.70
1775.70
1775.70
1775.70
1775.70
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
823.50
691.70
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
-1779.30
-1779.30
-1779.30
-1779.30
-1779.30
-1779.30
-1779.30
-1779.30
-1779.30
-1690.00
-1690.00
-1690.00
-1430.20
-1294.80
-1149.50
-1013.90
-872.80
-149.00
-277.00
-1712.30
-1712.30
-1712.30
-1411.10
-1283.10
-1151.30
-1023.30
-891.50
-763.50
-631.70
-503.70
-371.90
-243.90
-112.10
15.90
563.70
-408.80
431.90
-536.80
303.90
-668.60
172.10
-796.60
44.10
-928.80
-1056.80
-1189.00
-1375.40
-1515.40
-1651.00
-1599.90
-1599.90
-1599.90
-1599.90
-1600.00
-1600.00
-1600.00
-1600.00
-87.70
-215.70
-347.50
-475.50
-607.30
-735.30
-867.10
-995.10
-1126.90
-1254.90
-1386.70
-1514.70
-1646.50
147.70
275.70
407.50
-738.30
535.50
-600.10
667.30
-465.60
Pad Description
Pad No.
Pad Name
I/O
Description
Chip selection input with pull-high resistor. When the CS is logic high, the
data and command read from or write to the HT1647 are disabled. The serial
interface circuit is also reset. But if the CS is at a logic low level and is input to
the CS pad, the data and command transmission between the host control-
ler and the HT1647 are all enabled.
23
CS
I
READ clock input with pull-high resistor. Data in the RAM of the HT1647 are
clocked out on the rising edge of the RD signal. The clocked out data will ap-
pear on the data line. The host controller can use the next falling edge to
latch the clocked out data.
24
25
RD
I
I
WRITE clock input with pull-high resistor. Data on the DATA line are latched
into the HT1647 on the rising edge of the WR signal.
WR
26~29
30
DB0~DB3
VSS
I/O Parallel data input/output with a pull-high resistor
Negative power supply for logic circuit, ground
¾
31
OSCI
I
The OSCI and OSCO pads are connected to a 32.768kHz crystal in order to
generate a system clock. If the system clock comes from an external clock
source, the external clock source should be connected to the OSCI pad. But
if an on-chip RC oscillator is selected, the OSCI and OSCO pads can be left
open.
32
OSCO
O
33
VDD
Positive power supply for logic circuit
Power supply for LCD driver circuit
¾
I
34
VLCD
35
IRQ
O
O
I
Time base or Watchdog Timer overflow flag, NMOS open drain output.
2kHz or 4kHz frequency output pair (tristate output buffer)
Not connected
36, 37
38~41
42~57
BZ, BZ
T1~T4
COM0~COM15
O
LCD common outputs
58~99,
1~22
SEG0~SEG63
O
LCD segment outputs
Rev. 1.30
4
November 10, 2005
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
