PATENTED
Pad Assignment
S E G 3 1
5 4
1
2
3
4
S
C I
D
D
Q
6
7
8
9
1 0
(0 ,0 )
B Z
5
S E G 3 0
5 3
S E G 2 9
5 2
S E G 2 7
S E G 2 8
5 1 5 0
S E G 2 6
4 9
S E G 2 5
4 8
S E G 2 4
4 7
S E G 2 3
4 6
S E G 2 2
4 5
S E G 2 1
4 4
S E G 2 0
4 3
HT1622
C S
R D
W R
D A T A
V S
O S
V D
V L C
IR
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
1 9
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
1 0
S E G 9
S E G 8
S E G 7
B Z
T 1
T 2
T 3
C O M 0
C O M 1
1 1
1 2
1 3
1 4
1 5
1 6
1 7
C O M 2
1 8
C O M 3
1 9
C O M 4
2 0
C O M 5
2 1 2 2
C O M 7
C O M 6
2 3
S E G 0
2 4
S E G 1
2 5
S E G 2
2 6
2 7 2 8
S E G 5
2 9
S E G 6
S E G 4
S E G 3
Chip size: 94
´
98 (mil)
2
Bump height: 18mm
±
3mm
Min. Bump spacing: 23.102mm
Bump size: 76
´
76mm
2
* The IC substrate should be connected to VDD in the PCB layout artwork.
Rev. 2.00
3
June 9, 2009
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
