PATENTED
HT1622
Functional Description
remain at logic low level until the CLR WDT or the IRQ
DIS command is issued.
Display Memory - RAM Structure
The static display RAM is organized into 64´4 bits and
stores the display data. The contents of the RAM are di-
rectly mapped to the contents of the LCD driver. Data in
the RAM can be accessed by the READ, WRITE and
READ-MODIFY-WRITE commands. The following is a
mapping from the RAM to the LCD patterns.
If an external clock is selected as the source of system
frequency, the SYS DIS command turns out invalid and
the power down mode fails to be carried out until the ex-
ternal clock source is removed.
Buzzer Tone Output
Time Base and Watchdog Timer (WDT)
A simple tone generator is implemented in the HT1622.
The tone generator can output a pair of differential driv-
ing signals on the BZ and BZ which are used to generate
a single tone.
The time base generator and WDT share the same di-
vided (¸256) counter. TIMER DIS/EN/CLR, WDT
DIS/EN/CLR and IRQ EN/DIS are independent from each
other. Once the WDT time-out occurs, the IRQ pin will
C
O
M
C
7
O
M
C
6
O
M
C
5
O
M
4
C
O
M
C
3
O
M
C
2
O
M
C
1
O
M
0
S
S
S
S
E
E
E
E
G
G
G
G
0
1
2
3
1
3
5
7
0
2
4
6
A
d
d
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e
s
s
6
(
A
5
,
A
4
,
.
S
E
G
3
1
6
3
6
2
A
d
d
r
A
d
d
r
D
3
D
2
D
1
D
0
D
3
D
2
D
1
D
0
D
a
t
a
D
a
t
a
D
a
t
a
4
B
i
t
s
(
D
3
,
D
2
,
D
1
,
D
0
)
RAM Mapping
T
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B
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I
R
Q
T
I
M
E
R
E
N
/
D
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¸
2
5
6
c e
C
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o
c
k
S
o
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W
D
D
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N
/
D
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V
D
C
L
R
T
i
m
e
r
Q
D
W
D
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I
R
Q
E
N
/
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4
C
K
R
C
L
R
W
D
T
Timer and WDT Configurations
Rev. 2.00
8
June 9, 2009
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
