PATENTED
HT1626
A.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
Conditions
fSYS1
fSYS2
fLCD1
fLCD2
tCOM
System Clock
5V On-chip RC oscillator
24
¾
48
¾
¾
4
32
32
40
¾
kHz
kHz
Hz
System Clock
External clock source
5V On-chip RC oscillator
¾
LCD Frame Frequency
LCD Frame Frequency
LCD Common Period
64
80
External clock source
n: Number of COM
64
Hz
¾
¾
¾
n/fLCD
sec
kHz
kHz
kHz
kHz
¾
3V
5V
3V
5V
150
300
75
¾
¾
¾
¾
fCLK1
Serial Data Clock (WR Pin)
Serial Data Clock (RD Pin)
Duty cycle 50%
4
¾
¾
fCLK2
Duty cycle 50%
CS
150
Serial Interface Reset Pulse Width
(Figure 3)
tCS
500
600
ns
¾
¾
Write mode
Read mode
Write mode
Read mode
3.34
6.67
1.67
3.34
125
¾
¾
¾
¾
¾
3V
ms
WR, RD Input Pulse Width
(Figure 1)
tCLK
125
¾
5V
ms
Rise or Fall Time Serial Data Clock
Width (Figure 1)
tr, tf
120
120
600
600
100
160
¾
ns
ns
ns
ns
ns
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
60
Setup Time for DATA to WR, RD
Clock Width (Figure 2)
tsu
Setup Time for CS to WR, RD
Clock Width (Figure 3)
tsu1
500
500
50
¾
Hold Time for DATA to WR, RD
Clock Width (Figure 2)
th
¾
Hold Time for CS to WR, RD Clock
Width (Figure 3)
th1
¾
Tone Frequency (2kHz)
1.5
3.0
20
2.0
4.0
¾
2.5
5.0
¾
kHz
kHz
ms
fTONE
5V On-chip RC oscillator
Tone Frequency (4kHz)
tOFF
tSR
VDD OFF Times (Figure 4)
VDD Rising Slew Rate (Figure 4)
VDD drop down to 0V
¾
¾
¾
0.05
1
V/ms
ms
¾
¾
¾
tRSTD
Delay Time after Reset (Figure 4)
¾
¾
¾
Note: 1. If the conditions of Power-on Reset timing are not satisfied in power On/Off sequence, the internal
Power-on Reset (POR) circuit will not operate normally.
2. If the VDD drops below the minimum voltage of operating voltage spec. during operating, the conditions
of Power-on Reset timing must be satisfied also. That is, the VDD must drop to 0V and keep at 0V for
20ms (min.) before rising to the normal operating voltage.
Rev. 1.60
7
November 9, 2010
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
