PATENTED
A.C. Characteristics
Symbol
f
SYS1
f
SYS2
f
LCD1
f
LCD2
t
COM
f
CLK1
System Clock
System Clock
LCD Frame Frequency
LCD Frame Frequency
LCD Common Period
Serial Data Clock (WR Pin)
5V
f
CLK2
3V
Serial Data Clock (RD Pin)
5V
t
CS
Serial Interface Reset Pulse Width
(Figure 3)
¾
3V
t
CLK
Read mode
WR, RD Input Pulse Width (Figure 1)
Write mode
5V
Read mode
t
r
, t
f
t
su
t
h
t
su1
t
h1
f
TONE
t
OFF
t
SR
Note:
Rise/Fall Time Serial Data Clock Width
(Figure 1)
Setup Time DATA to WR, RD Clock
Width (Figure 2)
Hold Time DATA to WR, RD Clock Width
(Figure 2)
Setup Time for CS to WR, RD Clock
Width (Figure 3)
Hold Time for CS to WR, RD Clock Width
(Figure 3)
Tone Frequency (2kHz)
5V
Tone Frequency (4kHz)
V
DD
OFF Times (Figure 4)
V
DD
Rising Slew Rate (Figure 4)
¾
¾
VDD drop down to 0V
¾
On-chip RC oscillator
3.0
20
0.05
4.0
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
3.34
¾
60
1000
500
50
1.5
1.67
6.67
CS
Write mode
Duty cycle 50%
Parameter
Test Conditions
V
DD
5V
¾
5V
¾
¾
3V
Duty cycle 50%
4
¾
¾
700
3.34
Conditions
On-chip RC oscillator
External clock source
On-chip RC oscillator
External clock source
n: Number of COM
Min.
24
¾
48
¾
¾
4
Typ.
32
32
64
64
n/f
LCD
¾
¾
¾
¾
800
¾
¾
¾
¾
120
120
1200
600
100
2.0
HT1623
Ta=25°C
Max.
40
¾
80
¾
¾
150
300
75
150
¾
125
¾
125
¾
160
¾
¾
¾
¾
2.5
5.0
¾
¾
Unit
kHz
kHz
Hz
Hz
sec
kHz
kHz
kHz
kHz
ns
ms
ms
ns
ns
ns
ns
ns
kHz
kHz
ms
V/ms
1. If the conditions of Power-on Reset timing are not satisfied in power On/Off sequence, the internal
Power-on Reset (POR) circuit will not operate normally.
2. If the VDD drops below the minimum voltage of operating voltage spec. during operating, the conditions
of Power-on Reset timing must be satisfied also. That is, the VDD must drop to 0V and keep at 0V for
20ms (min.) before rising to the normal operating voltage.
Rev. 1.50
7
June 17, 2009
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
