PATENTED
A.C. Characteristics
Symbol
f
SYS1
f
SYS2
f
SYS3
Parameter
System Clock
System Clock
System Clock
Test Conditions
V
DD
3V
¾
¾
¾
f
LCD
LCD Clock
¾
¾
t
COM
f
CLK1
LCD Common Period
Serial Data Clock (WR pin)
5V
f
CLK2
3V
Serial Data Clock (RD pin)
5V
f
TONE
t
CS
Tone Frequency (2kHz)
3V
Tone Frequency (4kHz)
Serial Interface Reset Pulse
Width (Figure 3)
¾
3V
t
CLK
WR, RD Input Pulse Width
(Figure 1)
5V
Read mode
t
r
, t
f
t
SU
t
h
t
su1
t
h1
t
OFF
t
SR
t
RSTD
Note:
Rise/Fall Time Serial Data Clock
Width (Figure 1)
Setup Time for DATA to WR, RD
Clock Width (Figure 2)
Hold Time for DATA to WR, RD
Clock Width (Figure 2)
Setup Time for CS to WR, RD
Clock Width (Figure 3)
Hold Time for CS to WR, RD Clock
Width (Figure 3)
V
DD
OFF Times (Figure 4)
V
DD
Rising Slew Rate (Figure 4)
Delay Time after Reset (Figure 4)
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
V
DD
drop down to 0V
¾
¾
3.34
¾
60
250
500
50
20
0.05
1
Read mode
Write mode
6.67
1.67
CS
Write mode
On-chip RC oscillator
3.0
250
3.34
Duty cycle 50%
¾
3V
Duty cycle 50%
4
¾
¾
1.5
Conditions
On-chip RC oscillator
Crystal oscillator
External clock source
On-chip RC oscillator
Crystal oscillator
External clock source
n: Number of COM
Min.
192
¾
¾
¾
¾
¾
¾
4
HT1621/HT1621G
Ta=25°C
Typ.
256
32768
256
f
SYS1
/1024
f
SYS2
/128
f
SYS3
/1024
n/f
LCD
¾
¾
¾
¾
2.0
4.0
300
¾
¾
¾
¾
120
120
300
600
100
¾
¾
¾
Max.
320
¾
¾
¾
¾
¾
¾
150
300
75
150
2.5
5.0
¾
125
¾
125
¾
160
¾
¾
¾
¾
¾
¾
¾
Unit
kHz
Hz
kHz
Hz
Hz
Hz
s
kHz
kHz
kHz
kHz
kHz
kHz
ns
ms
ms
ns
ns
ns
ns
ns
ms
V/ms
ms
1. If the conditions of Power-on Reset timing are not satisfied in power On/Off sequence, the internal
Power-on Reset (POR) circuit will not operate normally.
2. If the VDD drops below the minimum voltage of operating voltage spec. during operating, the conditions
of Power-on Reset timing must be satisfied also. That is, the VDD must drop to 0V and keep at 0V for
20ms (min.) before rising to the normal operating voltage.
Rev. 2.90
6
November 9, 2010
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
