PATENTED
t
f
W R , R D
C lo c k
9 0 %
5 0 %
1 0 %
t
r
V
t
C
L K
D D
HT1626
V A L ID D A T A
V
t
h
u
D D
t
C
G N D
D B
5 0 %
t
s
L K
G N D
V
D D
Figure 1
W R , R D
C lo c k
5 0 %
G N D
Figure 2
t
C
S
V D D
V
D D
C S
5 0 %
t
s
u 1
t
S
R
0 .9 V
D D
t
h
1
G N D
V
D D
0 V
t
O
F F
W R , R D
C lo c k
5 0 %
F IR S T
C lo c k
t
R
S T D
L A S T
C lo c k
G N D
Figure 3
C S
Figure 4. Power-on Reset Timing
Functional Description
Display Memory
-
RAM Structure
The static display RAM is organized into 192´4 bits and
stores the display data. The contents of the RAM are di-
rectly mapped to the contents of the LCD driver. Data in
the RAM can be accessed by the READ, WRITE and
READ-MOD-
IFY-WRITE commands. The following is a mapping from
the RAM to the LCD patterns.
Time Base and Watchdog Timer
-
WDT
The time base generator and WDT share the same di-
vided (/256) counter. TIMER DIS/EN/CLR, WDT
DIS/EN/CLR and IRQ EN/DIS are independent from each
other. Once the WDT time-out occurs, the IRQ pin will
remain at logic low level until the CLR WDT or the IRQ
DIS command is issued.
C O M 1 5
S E G 0
S E G 1
S E G 2
S E G 3
7
1 1
1 5
8
1 2
A d d r e s s 8 B its
(A 7 , A 6 , ...., A 0 )
C O M 1 4
C O M 1 3
C O M 1 2
3
4
If an external clock is selected as the source of system
frequency, the SYS DIS command turns out invalid and
the power down mode fails to be carried out until the ex-
ternal clock source is removed.
Buzzer Tone Output
A simple tone generator is implemented in the HT1626.
The tone generator can output a pair of differential driv-
ing signals on the BZ and BZ which are used to generate
a single tone.
Command Format
The HT1626 can be configured by the software setting.
There are two mode commands to configure the
HT1626 resource and to transfer the LCD display data.
C O M 3
C O M 2
C O M 1
C O M 0
0
S E G 4 7
D 3
D 2
D 1
D 0
1 9 1
A d d r
D a ta
D 3
D 2
D 1
D 0
1 8 8
A d d r
D a ta
D a ta 4 B its
(D 3 , D 2 , D 1 , D 0 )
RAM Mapping
Rev. 1.60
8
November 9, 2010
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
