HT16270
V
A
L
I
D
D
A
T
A
V
G
D
D
D
B
5
0
%
t
f
t
r
N
D
-
V
D
D
t
s
u
t
h
W
C
R
,
R
D
0 %
9
5
k
1
0
%
l
o
c
G
N
D
0
%
V
G
D
D
t
C
L
K
t
C
L
K
W
C
R
,
R
D
5
0
%
l
o
c
k
-
N
D
Figure 1
Figure 2
t
C
S
-
-
V
V
D
D
D
D
C
S
5
0
%
G
G
N
N
D
D
t
s
u
1
t
h
1
W
C
R
,
R
D
5
0
%
l
o
c
k
F
I
R
S
T
L
C
A
S
T
C
l
o
c
k
l
o
c
k
Figure 3
Functional Description
Display memory - RAM structure
Time base and watchdog timer - WDT
The time base generator and WDT share the
same divided (/256) counter. TIMER DIS/EN/CLR,
WDT DIS/EN/CLR and IRQ EN/DIS are inde-
pendent from each other. Once the WDT
time-out occurs, the IRQ pin will remain at
logic low level until the CLR WDT or the IRQ
DIS command is issued.
The static display RAM is organized into 256´4
bits and stores the display data. The contents of
the RAM are directly mapped to the contents of
the LCD driver. Data in the RAM can be
a c c e s s e d b y t h e R E A D , W R I T E a n d
READ-MODIFY-WRITE commands. The fol-
lowing is a mapping from the RAM to the LCD
patterns.
C
O
M
C
1
O
5
M
C
1
O
4
M
C
1
O
3
M
1
2
C
O
M
C
3
O
M
C
2
O
M
C
1
O
M
0
S
S
S
S
E
E
E
E
G
G
G
G
0
1
2
3
3
7
0
4
8
1
1
1
5
A
d
d
r
e
s
s
8
B
i
t
s
1
2
(
A
7
,
A
6
,
.
.
.
.
,
A
0
)
S
E
G
6
3
2
5
5
2
5
2
A
d
d
r
A
d
d
r
D
3
D
2
D
1
D
0
D
3
D
2
D
1
D
0
D
a
t
a
D
a
t
a
D
a
t
a
4
B
i
t
s
(
D
3
,
D
2
,
D
1
,
D
0
)
RAM mapping
8
April 21, 2000
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
