HT1625
V A L ID D A T A
V
t
h
u
D D
t
f
W R , R D
C lo c k
9 0 %
5 0 %
1 0 %
t
r
V
t
C
L K
D B
D D
5 0 %
t
s
G N D
V
D D
t
C
G N D
W R , R D
C lo c k
5 0 %
L K
G N D
Figure 1
t
C
S
Figure 1
C S
5 0 %
t
s
u 1
V
D D
t
h
1
G N D
V
D D
W R , R D
C lo c k
5 0 %
F IR S T
C lo c k
L A S T
C lo c k
G N D
Figure 2
Functional Description
Display memory
-
RAM structure
The static display RAM is organized into 128´4
bits and stores the display data. The contents of
the RAM are directly mapped to the contents of
the LCD driver. Data in the RAM can be ac-
cessed by the READ, WRITE and READ-MOD-
IFY-WRITE commands. The following is a map-
ping from the RAM to the LCD patterns.
C O M 7
S E G 0
S E G 1
S E G 2
S E G 3
7
5
6
3
4
A d d r e s s 7 B its
(A 6 , A 5 , ...., A 0 )
C O M 6
C O M 5
C O M 4
1
2
C O M 3
Time base and Watchdog Timer
-
WDT
The time base generator and WDT share the
same divided (/256) counter. TIMER DIS/EN/CLR
, WDT DIS/EN/CLR and IRQ EN/DIS are inde-
pendent from each other. Once the WDT
time-out occurs, the IRQ pin will remain at
logic low level until the CLR WDT or the IRQ
DIS command is issued.
C O M 2
C O M 1
C O M 0
0
S E G 6 3
D 3
D 2
D 1
D 0
1 2 7
A d d r
D a ta
D 3
D 2
D 1
D 0
1 2 6
A d d r
D a ta
D a ta 4 B its
(D 3 , D 2 , D 1 , D 0 )
RAM mapping
8
April 21, 2000
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
