HT1622
V
A
L
I
D
D
A
T
A
V
G
D
D
t
t
r
D
B
5
0
%
f
V
G
D
D
D
D
N
N
9
0
%
D
W
C
R
,
R
t
t
h
5
0
%
s
u
l
o
c
k
1
D
N
0
%
t
t
C
C
L
K
L
K
V
G
D
D
W
C
R
,
R
D
5
0
%
l
o
c
k
Figure 1
Figure 2
t
C
S
V
G
D
D
5
0
%
C
S
N
N
D
D
t
t
h
s
u
1
1
V
G
D
D
W
C
R
,
R
D
5
0
%
l
o
c
k
F
I
R
S
T
L
C
A
S
T
C
l
o
c
k
l
o
c
k
Figure 3
Functional Description
Time base and Watchdog Timer (WDT)
Display memory - RAM structure
The time base generator and WDT share the
same divided (/256) counter. TIMER
DIS/EN/CLR, WDT DIS/EN/CLR and IRQ
EN/DIS are independent from each other. Once
the WDT time-out occurs, the IRQ pin will re-
main at logic low level until the CLR WDT or
the IRQ DIS command is issued.
The static display RAM is organized into 64´4
bits and stores the display data. The contents of
the RAM are directly mapped to the contents of
the LCD driver. Data in the RAM can be ac-
cessed by the READ, WRITE and
READ-MODIFY-WRITE commands. The fol-
lowing is a mapping from the RAM to the LCD
patterns.
C
O
M
C
7
O
M
C
6
O
M
C
5
O
M
4
C
O
M
C
3
O
M
C
2
O
M
C
1
O
M
0
S
S
S
S
E
E
E
E
G
G
G
G
0
1
2
3
1
3
5
7
0
2
4
6
A
d
d
r
e
s
s
6
B
i
t
s
(
A
5
,
A
4
,
.
.
.
.
,
A
0
)
S
E
G
3
1
6
3
6
2
A
d
d
r
A
d
d
r
D
3
D
2
D
1
D
0
D
3
D
2
D
1
D
0
D
a
t
a
D
a
t
a
D
a
t
a
4
B
i
t
s
(
D
,
3
D
,
2
D
,
1
D
)
0
RAM mapping
8
April 21, 2000
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
