HT16270
V A L ID D A T A
D B
V
t
h
u
D D
t
f
W R , R D
C lo c k
9 0 %
5 0 %
1 0 %
t
r
5 0 %
t
s
-
V
t
C
L K
D D
G N D
V
D D
t
C
L K
G N D
W R , R D
C lo c k
5 0 %
-
G N D
Figure 1
t
C
S
Figure 2
C S
5 0 %
t
s
u 1
-
V
D D
t
h
1
G N D
-
V
D D
W R , R D
C lo c k
5 0 %
F IR S T
C lo c k
L A S T
C lo c k
G N D
Figure 3
Functional Description
Display memory
-
RAM structure
The static display RAM is organized into 256´4
bits and stores the display data. The contents of
the RAM are directly mapped to the contents of
the LCD driver. Data in the RAM can be
accessedbytheREAD,WRITEand
READ-MODIFY-WRITE commands. The fol-
lowing is a mapping from the RAM to the LCD
patterns.
C O M 1 5
S E G 0
S E G 1
S E G 2
S E G 3
7
1 1
1 5
8
1 2
A d d r e s s 8 B its
(A 7 , A 6 , ...., A 0 )
C O M 1 4
C O M 1 3
C O M 1 2
3
4
Time base and watchdog timer
-
WDT
The time base generator and WDT share the
same divided (/256) counter. TIMER DIS/EN/CLR,
WDT DIS/EN/CLR and IRQ EN/DIS are inde-
pendent from each other. Once the WDT
time-out occurs, the IRQ pin will remain at
logic low level until the CLR WDT or the IRQ
DIS command is issued.
C O M 3
C O M 2
C O M 1
C O M 0
0
S E G 6 3
D 3
D 2
D 1
D 0
2 5 5
A d d r
D a ta
D 3
D 2
D 1
D 0
2 5 2
A d d r
D a ta
D a ta 4 B its
(D 3 , D 2 , D 1 , D 0 )
RAM mapping
8
April 21, 2000
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
