HT1380/HT1381
The following diagram shows the single and burst mode transfer:
S
i
n
g
l
e
b
y
t
e
t
r
a
n
s
f
e
r
S
C
L
K
R
E
S
T
0
1
2
3
4
5
6
7
0
1
I
/
O
0
R
/
W
A
0
A
1
A
2
0
0
1
C
O
M
M
A
N
D
B
Y
T
D
E
A
T
A
I
/
O
B
u
r
s
t
m
o
d
e
t
r
a
n
s
f
e
r
S
C
L
K
R
E
S
T
0
1
2
0
7
3
0
4
7
5
6
7
I
/
O
R
/
W
1
1
1
1
0
1
1
C
O
M
M
A
N
D
D
B
A
Y
T
T
A
E
B
Y
T
E
0
D
A
T
A
B
Y
T
E
7
The table illustrates the values suggested for capacities C1, C2
Part No.
Crystal Error
±10ppm
Capacity Value
5pF
8pF
HT1380/HT1381
10~20ppm
Operating flowchart
To initiate any transfer of data, REST is taken high and an 8-bit command byte is first loaded into the
control logic to provide the register address and command information. Following the command
word, the clock/calendar data is serially transferred to or from the corresponding register. The REST
pin must be taken low again after the transfer operation is completed. All data enter on the rising
edge of SCLK and outputs on the falling edge of SCLK. In total, 16 clock pulses are needed for a sin-
gle byte mode and 72 for burst mode. Both input and output data starts with bit 0.
In using the HT1380/HT1381, set first the WP and CH to 0 and wait for about 3 seconds, the oscilla-
tor will generate the clocks for internal use. Then, choose either single mode or burst mode to input
the data. The read or write operating flowcharts are shown on the next page.
7
September 18, 2000
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
