HT1380/HT1381
The following table shows the register address and its data format:
Register
Name
Seconds
Minutes
Hours
Date
Month
Day
Year
Write
Protect
Range
Data
00~59
00~59
01~12
00~23
01~31
01~12
01~07
00~99
00~80
WP
Register Definition
D7
CH
0
12\
24
0
0
0
0
0
0
0
0
D6
D5
10 SEC
10 MIN
AP
10
HR
HR
D4
D3
D2
D1
Address
D0 A2~A0
000
001
010
011
100
101
110
111
Bit
R/W
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
Command
Byte
10000000
10000001
10000010
10000011
10000100
10000101
10000110
10000111
10001000
10001001
10001010
10001011
10001100
10001101
10001110
10001111
SEC
MIN
HOUR
DATE
MONTH
DAY
YEAR
10 DATE
0
0
10M
0
10 YEAR
ALWAYS ZERO
CH: Clock Halt bit
CH=0 oscillator enabled
CH=1 oscillator disabled
WP: Write protect bit
WP=0 register data can be written in
WP=1 register data can not be written in
Bit 7 of Reg2: 12/24 mode flag
bit 7=1, 12-hour mode
bit 7=0, 24-hour mode
Bit 5 of Reg2: AM/PM mode defined
AP=1 PM mode
AP=0 AM mode
R/W signal
The LSB of the Command Byte determines
whether the data in the register be read or be
written to.
When it is set as
²0²
means that a write cycle is
to take place otherwise this chip will be set into
the read mode.
A0~A2
A0 to A2 of the Command Byte is used to specify
which registers are to be accessed. There are
eight registers used to control the month data,
etc., and each of these registers have to be set as
a write cycle in the initial time.
Burst mode
When the Command Byte is 10111110 (or
10111111), the HT1380/HT1381 is configured in
burst mode. In this mode the eight clock/calen-
dar registers can be written (or read) in series,
starting with bit 0 of register address 0 (see the
timing on the next page).
Test mode
When the Command Byte is set as 1001xxx1,
HT1380/HT1381 is configured in test mode.
The test mode is used by Holtek only for testing
purposes. If used generally, unpredictable con-
ditions may occur.
5
September 18, 2000
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
