HT1350
Pad Assignment
A U T O /M A N U
W A L K /R U N
R E S E T
T E S T 3
M O D E
V D D
V S S
T E S T 2
1
2
3
T E S T 1
O S C 2
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
2 4
O S C 1
O U T 1 7
O U T 1 6
6
7
8
9
O U T 1 3
1 0
O U T 1 2
1 1
O U T 1 1
2 0
O U T 1 5
O U T 1 4
5
4
(0 ,0 )
2 3
2 2
2 1
S T E P
C P 1
C P 2
C P 3
C O M 1
C O M 2
1 2
O U T 1 0
1 3
O U T 9
1 4
O U T 8
1 5
O U T 7
1 6
O U T 6
1 7
O U T 5
1 8
O U T 4
1 9
C O M 3
Chip size: 2725
´
2780 (mm)
2
* The IC substrate should be connected to VDD in the PCB layout artwork.
Unit:
mm
Pad No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
X
-1206.00
-1206.00
-1206.00
-1206.00
-1206.00
-1206.00
-1206.00
-1206.00
-1098.00
-898.00
-633.00
-433.00
-168.00
32.00
297.00
497.00
Y
1159.50
994.50
661.70
71.50
-159.50
-359.50
-624.50
-824.50
-1190.50
-1190.50
-1190.50
-1190.50
-1190.50
-1190.50
-1190.50
-1190.50
2
Pad No.
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
X
762.00
962.00
1202.00
1202.00
1202.00
1202.00
1202.00
1202.00
1202.00
1078.00
812.00
631.00
447.00
-59.00
-259.00
-966.00
Y
-1190.50
-1190.50
-1190.50
-753.50
-335.50
-135.50
65.50
259.50
537.00
1167.50
1167.50
1167.50
1167.50
1167.50
1167.50
1167.50
June 28, 1999
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
