HT12D/HT12F
Block Diagram
O
S
C
O
2
S
C
1
O
s
c
i
l
l
a
t
D
o
i
r
v
i
d
e
r
D
a
t
a
S
h
i
f
t
D
a
t
a
u i
L
a
t
c
h
C
i
r
c
t
R
e
g
i
s
t
e
r
B
u
f
f
e
r
D
a
t
a
D
e
t
e
c
t
o
r
D
I
N
S
y
n
c
.
D
C
e
o
t
e
m
c
p
t
a
o
r
r
a
t
C
o
o
r
m
p
a
r
a
C
t
o
o
n
r
t
r
o
l
L
o
g
i
c
T
r
a
n
s
m
i
s
s
i
o
n
G
a
t
e
C
B
i
u
r
c
f
f
u
e
i
r
t
V
T
A
d
d
r
e
s
s
V
D
D
V
S
S
Note: The address/data pins are available in various combinations (see the address/data table).
Pin Assignment
8
-
A
d
d
r
e
s
s
1
2
-
A
d
d
r
e
s
s
1
2
-
A
d
d
r
e
s
s
8
-
A
d
d
r
e
s
s
4
-
D
a
t
a
0
-
D
a
t
a
0
-
D
a
t
a
4
-
D
a
t
a
N
C
2
1
1
1
1
1
1
1
1
1
0
9
8
7
6
5
4
3
2
1
N
C
2
1
1
1
1
1
1
1
1
1
0
9
8
7
6
5
4
3
2
1
N
V
V
O
O
D
D
D
D
D
C
N
V
V
O
O
D
A
A
A
A
C
1
2
3
4
5
6
7
8
9
1
1
2
3
4
5
6
7
8
9
1
1
2
3
4
5
6
7
8
9
1
1
1
1
1
1
1
1
1
8
7
6
5
4
3
2
1
0
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
9
1
1
1
1
1
1
1
1
1
8
7
6
5
4
3
2
1
0
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
V
V
O
O
D
D
D
D
D
D
T
D
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
V
V
O
O
D
A
A
A
A
D
T
D
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
D
T
D
D
T
D
S
S
C
C
1
2
S
S
C
C
1
2
S
S
C
C
1
2
S
S
C
C
1
2
I
1
1
9
8
N
I
N
I
1
1
9
8
N
I
N
1
0
1
1
9
8
1
0
1
0
1
1
9
8
1
0
V
S
S
V
S
S
V
S
S
V
S
S
0
0
H
T
1
2
D
H
T
1
2
F
H
T
1
2
D
H
T
1
2
F
2
0
S
O
P
-
A
2
0
S
O
P
1
8
D
I
P
-
A
1
8
D
I
P
-
A
Pin Description
Internal
Connection
Pin Name
I/O
Description
Input pins for address A0~A11 setting
A0~A11 (HT12F)
A0~A7 (HT12D)
These pins can be externally set to VSS or left open.
NMOS
I
Transmission Gate
Input pins for address A0~A7 setting
These pins can be externally set to VSS or left open.
D8~D11 (HT12D)
O
I
CMOS OUT
CMOS IN
CMOS OUT
Oscillator
Oscillator
¾
Output data pins, power-on state is low.
Serial data input pin
DIN
VT
O
I
Valid transmission, active high
Oscillator input pin
OSC1
OSC2
VSS
VDD
O
¾
¾
Oscillator output pin
Negative power supply, ground
Positive power supply
¾
Rev. 1.20
2
February 20, 2009
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
