HT46R14
A.C. Characteristics
Symbol
Parameter
Test Conditions
V
DD
¾
¾
¾
¾
3V
Watchdog Oscillator Period
5V
t
RES
t
SST
t
INT
t
AD
t
ADC
t
ADCS
t
COMP
External Reset Low Pulse Width
System Start-up Timer Period
Interrupt Pulse Width
A/D Clock Period
A/D Conversion Time
A/D Sampling Time
Comparator Response Time
¾
¾
¾
¾
¾
¾
¾
Conditions
2.2V~5.5V
3.3V~5.5V
2.2V~5.5V
3.3V~5.5V
¾
¾
¾
Power-up or Wake-up
from HALT
¾
¾
¾
¾
¾
Min.
400
400
0
0
45
32
1
¾
1
1
¾
¾
¾
Typ.
¾
¾
¾
¾
90
65
¾
1024
¾
¾
76
32
¾
Max.
4000
8000
4000
8000
180
130
¾
¾
¾
¾
¾
¾
3
Ta=25°C
Unit
kHz
kHz
kHz
kHz
ms
ms
ms
*t
SYS
ms
ms
t
AD
t
AD
ms
f
SYS
System Clock
Timer I/P Frequency
(TMR0/TMR1)
f
TIMER
t
WDTOSC
Note: *t
SYS
=1/f
SYS
Functional Description
Execution Flow
The system clock for the microcontroller is derived from
either a crystal or an RC oscillator. The system clock is
internally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while de-
coding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruc-
tion to effectively execute in a cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
Program Counter
-
PC
The program counter (PC) controls the sequence in
which the instructions stored in program PROM are exe-
cuted and its contents specify full range of program
memory.
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are in-
cremented by one. The program counter then points to the
memory word containing the next instruction code.
When executing a jump instruction, conditional skip ex-
ecution, loading PCL register, subroutine call, initial re-
set, internal interrupt, external interrupt or return from
subroutine, the PC manipulates the program transfer by
loading the address corresponding to each instruction.
T 2
T 3
T 4
T 1
T 2
T 3
T 4
S y s te m
O S C 2 (R C
C lo c k
o n ly )
P C
T 1
T 2
T 3
T 4
T 1
P C
P C + 1
P C + 2
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Rev. 1.00
5
November 1, 2005
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
