HN705/HN706
DETAILED DESCRIPTON
RESET Operation
The RESET signals are designed to start a µP / µC in a
known state or return the system to a known state.
RESET is guaranteed to be LOW with V
CC
above 1.2V.
During a power-up sequence, RESET remains low until
the supply rises above the threshold level, either 4.65V
or 4.40V. RESET goes high approximately 200ms after
crossing the threshold.
During power-down, RESET goes LOW as V
CC
falls below
the threshold level and is guaranteed to be under 0.5V
with V
CC
above 1.2V.
In a brownout situation where V
CC
falls below the
threshold level, RESET pulses low. If a brownout occurs
during an already-initiated reset, the pulse will continue for
a minimum of 130ms.
Manual Reset (MR)
The active-LOW manual reset input is internally pulled up
to V
CC
with an internal impedance of 40K typical and can
be driven low by CMOS/TTL logic or a mechanical switch
to ground. An external debounce circuit is unnecessary
since the 130ms minimum reset time will debounce
mechanical pushbutton switches.
By connecting the watchdog output (WDO) and MR, a
watchdog timeout forces RESET to be generated.
Watchdog Timer
The watchdog timer function forces WDO signals active
when the WDI input is not clocked within the 1.6 second
time-out period. Time-out of the watchdog starts when
RST (or RST) becomes inactive. If a high-to-low transition
occurs on the WDI input pin prior to time-out, the
watchdog timer is reset and begins to time out again. If
the watchdog timer is allowed to time out, the WDO signal
is driven active (low) for a minimum of 130 ms. The WDI
input can be derived from many microprocessor outputs.
The typical signals used are the microprocessors address
signals, data signals, or control signals. When the
microprocessor functions normally, these signals would,
as a matter of routine, cause the watchdog to be reset
prior to time-out. To guarantee that the watchdog timer
does not time out, a high-to-low transition must occur at or
less than the minimum watchdog time-out of 1 second.
Auxiliary Comparator
All devices have an auxiliary comparator with 1.25V trip
point and uncommitted output (PFO) and noninverting
input (PFI). This comparator can be used as a supply
voltage monitor with an external resistor voltage divider.
The attenuated voltage at PFI should be set just below the
1.25 threshold. As the supply level falls, PFI is reduced
causing the PFO output to transit LOW. Normally PFO
interrupts the processor so the system can be shut down
in a controlled manner.
5V
WDI
0V
t
WD
t
WP
5V
t
WD
WDO
0V
t
WD
5V
RESET
0V
RESET triggered by MR
t
RS
(RESET)
IMP813L
0V
5V
Figure 2. Watchdog Timing
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座
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4
HN [ NANJING HONANO ELECTRONIC CO., LTD. ]
