HN1232
DETAILED DESCRIPTON
Power Monitor
The HN1232 detects out–of–tolerance power supply
conditions and warns a processor–based system of
impending power failure. When V
CC
falls below a preset
level as defined by TOL (Pin 3), the V
CC
comparator
outputs the signals RST (Pin 5) and RST (Pin 6). When
TOL is connected to ground, the RST and RST signals
become active as V
CC
falls below 4.75 volts. When TOL is
connected to V
CC
, the RST and RST signals become
active as V
CC
falls below 4.5 volts. The RST and RST are
excellent control signals for a microprocessor, as
processing is stopped at the last possible moments of
valid V
CC
. On power–up, RST and RST are kept active for
a minimum of 250 ms to allow the power supply and
processor to stabilize.
Pushbutton Reset Input
The debounced manual reset input (PBRST) manually
forces the reset outputs into their active states (Figure 1).
Once PBRST has been low for a time t
PDLY,
the
push-button delay time, the reset outputs go active. The
reset outputs remain in their active states for a minimum
of 250ms after PBRST rises above V
IH
(Figure 3).
A mechanical push-button or active logic signal can drive
the PBRST input. The debounced input ignores input
pulses less than 1ms and is guaranteed to recognize
pulses of 20ms or greater. No external pull-up resistor is
required because the PBRST input has an internal pull-up
to V
CC
of approximately 100µA.
Watchdog Timer
A watchdog timer function forces RST and RST signals
to the active state when the ST input is not stimulated for
a predetermined time period. The time period is set by
the TD input to be typically 150 ms with TD connected to
ground, 600 ms with TD left unconnected, and 1.2
seconds with TD connected to V
CC
. The watchdog timer
starts timing out from the set time period as soon as RST
and RST are inactive. If a high–to–low transition occurs
on the ST input pin prior to time–out, the watchdog timer
is reset and begins to time–out again. If the watchdog
timer is allowed to time-out, then the RST and RST
signals are driven to the active state for 250 ms
minimum.
The ST input can be derived from microprocessor
address signals, data signals, and / or control signals.
When the microprocessor is functioning normally, these
signals would, as a matter of routine, cause the
watch-dog to be reset prior to time–out. To guarantee
that the watchdog timer does not time–out, a
high–to–low transition must occur at or less than the
minimum shown in Table 1. A typical circuit example is
shown in Figure 2.
Watchdog Timeouts
Table 1
Watchdog Time-Out Period (ms)
TD Pin Voltage
Level
Min
Typ
Max
GND
62.5
150
250
Floating
250
600
1000
V
CC
500
1200
2000
5V
HN1232
1
5V
2
3
4
PBRST
TD
TOL
GND
V
CC
ST
RST
RST
8
7
6
5
I/O
8051 µP
RESET
Figure 1. Application Circuit: Pushbutton Reset
5V
HN1232
1
2
3
4
PBRST
TD
TOL
GND
V
CC
ST
RST
RST
8
7
6
5
10kΩ
MREQ
Ζ80 µP
RST
Address
Bus
Decoder
Figure 2. Application Circuit: Watchdog Timer
地址: 南京市珠江路
88
号，新世界中心
B
座
4004
室, 邮编:210008
ADD.: RM. 4004,
BLOCK B,
NEW WORLD CENTRE,
电话(TEL.):
(86)-25-68853600
NANJING 210008,
CHINA
传真(FAX):
(86)-25-68853600-810
WEB-SITE: WWW.HN-ELEC.COM
NO. 88 ZHUJIANG ROAD,
4
HN [ NANJING HONANO ELECTRONIC CO., LTD. ]
